AMD Opteron

Early on, slide 17 says that the Hammer/Athlon will have one 72-bit DDR channel which supports 200, 266 and 333 flavours of DDR up to four GB, quite similar to the description our reader gave us from Linuxworld earlier in the week.

Slide 36 shows the Opteron "glueless" SUMO multiprocessing model for these processors, with the next slide showing the "plumbing" to achieve good bandwidth using Hypertransport.

It's a lengthy 66 page set of slides but we are particularly interested in the plans that AMD seems to be cooking up on so-called Blade technology, which starts on page 58.

This slide says that AMD and other OEMs are working to create an open standard for "blades", slim servers, using cPCI and Hypertransport.

As part of that initiative, AMD will offer a low power Hammer that will offer 64-bit blades with system management and failover capabilities, as well as scale out an dhot swap, and network management.

It will also use this type of technology in SANs (storage area networks), high performance computing, and aim the products at telcos using a mobile telephone switch office, on demand content delivery and a recognition engine.

Eventually there will be an integrated dual processor too, the slide presentations suggests.

Slide 44 show the future chipset roadmap for Hammers and Athlon servers.

The slides also show an asymmetric 2P low cost desk top which has an Opteron as the foreground processor, supporting 8GB of memory, and a Clawhammer in the background, with some intergrated flash incorporated in it. (Slide 47)

There are block diagrams showing suggested models for fibrechannel storage servers and other configurations (slide 54), and something called a Quad AMD Opteron TCP/IP offload engine (slide 55).

In slide 57, there's a diagram of a "cubed" 8P server, and on slide 64 a nine channel GigE Firewall.

The Hypertransport back plane will support hot swaps (slide 65).

Chips that will support Hypertransport include Broadcom's dual MIPs processor, a PCI 66/64 bridge from SI Packets, which has API's legacy work, Nitrox security processor, and an FPGA from Xilinx and Altera. Infiniband, Fibrechannel and StarFabric bridges are all planned to support Hypertransport (slide 45).

This all looks very impressive