Intel Prescott die pictured

UPDATE Hans de Vries, at chip-architect.com, has now had a chance to compare this latest stepping die and has forwarded us an overlay. The image, here, is, he says not visibly different from the earliest Prescott images. The image, which is very large, is the new die with the macrocells of the older picture as an overlay. Hans has kindly given us permission to use the image.

Here's an excellent article Hans wrote in April last year demonstrating his evidence for the existence of 64-bit extensions inside the chip.

SORRY FOR the poor quality of this snap but I had to take a pic from a vendors' computer screen out here in Vegas.

It's a pic of the Prescott die, which uses Nickel Silicide rather than Cobat Silicide - a far more environmentally friendly and politically correct compound.

But it's a light metal with a low vapor point and that sorta stuff in fabs is no picnic, Jed tells me, plus the device physics are a whole new learning curve.

Also, says Jed, and I gotta take his word for this, high volume Nickel suffers from a lot of silicidation. Getting rid of Mr Cobalt is good, he says, because it's too resistive and way too rigid.

He had to guide us round the pic as well. He says Prescott might well have 64-bit capabilities in there. Why? Well, the pretty pretty two part upper and lower area in the center is the two 32-bit halves of the d-cache, the two 32-bit halves of the ALU (arithmetic logical unit) and the two 32-bit register banks which make up a 64-bit capable processor in the middle.

That's what Jed says anyway. And he's a tower of strength about this sort of thing.

Prescott is gonna launch in a few days time with 13 new instructions, 1MB of L2 cache, 16K of L1 data cache, 12K micro-ops of instruction cache, and at a die size around 112mm2, with the whole thing having over 124 million transistors. µ