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DRC Opteron accelerator now quickens Crays

More of them, many more
Tue May 02 2006, 14:16
A FEW MONTHS ago, we told you about AMD making accelerators, and then not too long after, a few of them peeked their little heads out.

DRC has a version that fits into an Opteron socket, basically doing all the things we said were 'really neato', and proving the point that an extensible stable platform is the only way forward. Now the company is hooking up with Cray to do roughly the same thing but on a larger scale.

Drc-coprocessor-on-an-opteron-mobo

Today, they are taking the standard DRC coprocessor, the one that plugs into an Opteron socket, and putting it directly on the Cray XD1 interconnect. The current DRC configurations let you plug one module into any open Opteron socket, so you can have a two way board with 1:1 Opteron to FPGA, a quad with 3:1 or 1:3, or an eight way with up to seven FPGAs. Cray then steps in and takes it to a whole new level.

The XD1 has nodes of 12 Opterons and puts 12 of those into a cabinet. For the math-impaired, that brings things to 144 CPUs per cabinet, and you can scale this out to a large number of cabinets. If you can only replace half of the CPUs with FPGAs, you still get 72 per cabinet, and that can bring a lot of horsepower to bear.

DRC claims that the FPGA are a huge speedup for specific algorithms, basically it will either work for you and work very well, or you should stick to vanilla Opterons. If your type of problem falls into the 'works' category, well, you get one heck of a bang for the buck. On an XD1, you get huge general purpose compute resources in a manageable physical space, and now you can add to it with the DRC boards.

The best part about all of this is that it takes less than a quarter of the power of an Opteron. With the FPGA in a supercomputer chassis, you get an order of magnitude or two speedup, and a large number of nodes to boot, pun intended. If the FPGA works for your algorithms, it can now scale about as large as you want it to go. µ

UPDATE: Cray now says that it is the XT3 machines that will get the DRC FPGA, not the XD1. The original release said XD1, but that is incorrect. Sorry for any confusion.

 

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