Dual cores and dual buses: The bolt-on story

OUR CHARLIE was very right when, last year, he pointed out that the initial dual-core Pentium stuff from Intel will be some kind of bolt-on rush job. At IDF, it became very obvious: Smithfield XE was basically two XeonDPs almost literally bolted together on one die. The standard Smithfield is the same, except HT is disabled, even with their separate bus interfaces, while the next round, Presler, is two separate CPU chips in one package.

So, in a way, neither of these is actually a dual-core CPU, like POWER5, Montecito or dual-core Opteron would be: Smithfield is a dual CPU chip, where two totally separate processors happen to share a single chip, and Presler is a dual-chip DCM (dual-chip module).

Shortcut to leadership
Well OK, whatever the means, as long as the results are there - Intel took a shortcut to claim the early lead in the dual CPU desktop race over AMD, even though the latter's CPU architecture is dual-core ready for quite some time. But there is certain cost involved: as The Inq readers know, two 3.2 GHz Prescott cores inside Smithfield will be faster than any other single-CPU Pentium if you happen to run Doom 3 and, say, Windows Media Encoder at the same time, however - for most current single-CPU optimised apps, a 3.46GHz Pentium 4 EE with the old Northwood core might still be faster, in the 32-bit mode at least. Its 1,066 MHz FSB will help a bit too - it is a problem for two bandwidth-hungry CPUs with just 1 MB cache each to compete for a single 800 MHz FSB, and it could cause bottlenecks if both "major" applications on the dual-core system happen to be memory-hungry.

Why only 800 MHz FSB when several current Pentium CPUs already have the 1,066 MHz one, and the overclockers proved this thingy could easily scale to 1,333 MHz throughput? Simply, it is a three-load bus, just like with Xeon DP dual-CPU systems, except that in this case, the situation is a bit simpler for the traces, as two CPU buses end in the same package. So, I believe Intel will be able to run this thing soon at 1,066 MHz FSB, but not much above that... the two load point-to-point link in standard Pentium 4 will always be able to clock faster for other variables assumed same.

Back to the future
When you look at the Dempsey/Bensley platform, which would be the Presler in XeonDP flavour, instead of adding extra bus load of second socket on the same FSB Hey, it would be a 5-load nightmare! Intel instead adds another FSB path in its north bridge, so that each dual-CPU DCM has its own 800 or 1,066 MHz FSB, feeding then on a wide multi-channel FB DIMM memory array. Well, we could also call this a crossbar - remember the six year old Alpha 21264 and its AlphaPC 264DP board? They had exactly this - separate paths for each CPU, then double-wide 512-bit memory bus to feed these two CPUs in parallel, six years ago. And yes, it was a 64-bit PC running Windows NT. A bit biiiiig-size PC with a 600W power supply, but guess what, we're about there now anyway.

Interestingly, the Paxville, a Xeon MP dual-core flavour, will instead be a single-chip dual CPU with a common bus interface! It is expected to be available at roughly the same time as Presler and Dempsey, so why not just use the Paxville core with its faster FSB potential in UP and DP systems, too? Or, maybe, it will become the next "Extreme Edition" there - if you notice, only the faster FSB now really distinguishes the Extreme from Standard CPUs .If excluding the one-off case with Smithfield where faster FSB wasn't possible, so they switched off HT in the Standard Edition.

Anyway, I'm still expecting my Smithfield XE, sorry, Pentium Extreme Edition sample that I can run at 1,066 MHz FSB. It would be lovely to see what effect a faster FSB has when it feeds two deeply-pipelined, bandwidth-starved Prescott cores, wouldn't it? I'd expect a 5%-10% across-the-board speedup for most dual-application scenarios - assuming we use CL3-3-3-9 or better DDR2-533 memory in both FSB cases (we gain a bit more due to synchronised FSB1066 to DDR2-533 operation). Your mileage may vary. µ