Rambus demos next-generation PCIe silicon

Using a 0.5 revision of proposed PCIe Gen2 standard, the company demonstrated working PCIe Gen2 controller in both software and hardware modes.

Using two PCBs and a lot of wires, engineers from Rambus managed to show working data transfer between two controllers. The silicon controllers were manufactured by TSMC, using 90 a nanometre node. Xilinx was also ever-present with its FPGA module in the role of controller which was sending data to another FPGA module via already mentioned Rambus controllers.

Target bandwidth is 5Gbps, which equals to 625 MB/s in one way - up from 250MB/s from the original PCIe 1.0 spec. If you calculate the bandwidth at x16, which we're used to seeing in the world of graphics, you can see that the available bandwidth for future residents of a PCIe x16 slot will jump from 8GB/s to the nice rounded figure of 20GB/s.

The spec should be finalised in Q107, and the first products will follow during the next calendar year. µ