IBM's Power 6 promises 5GHz boost

IBM HAS promised its partners that its Power 6 processors will hit between 4 to 5GHz pretty soon now, with each SMT2 core accessing 4MB of L2 memory, and sitting astirde a 32MB level three controller.

A Power 6 can thrust data of 64B/two cycles to Data Level One cache, with an aggregate L2 bandwidth of 127B/5 cycles per core. Data from the SMP fabric onto the chip will achieve 67 per cent times 40B/two cycles at peak.

A dual core chip will have nine execution units per core, with 790 million transistors on a 341 square millimetre die, with seven way superscalar performance and two memory controllers per chip, while it will be built on SOI 65 nanometre CMOS.

Big Glue will offer a whole series of alternate Power 6 bins, swapping cache depending on what customers want to build into their systems.

IBM claims that its 65 nanometer technology will offer a 30 per cent performance improvement over 90 nanometre chips, and use a a high performance SRAM cell.

The Power 6 core will have nine execution units, and reduces logic stages per cycle to 13FO4s to give higher frequencies.

Plus my boyfriend told me in his sleep that that 54 new instructions will include added arithmetic, comparison, test, convert, format and quantum adjustment instructions.

Let's hope Big Glue doesn't find out he's sleeping with me, because otherwise it would end what's a very cosy arrangement. Apart from him talking in his sleep that is. At least he doesn't snore, unlike that geezer from TMTA. µ