On Intel v AMD, Intel v Mac, Intel v 90nm

Subject: In a hole, Intel still digging
In your story "Late-coming Dothan set to arrive sporting 3G wirelessness" your apt question about the P4EE being a spoiler, along with his calculated answer of a question other than you asked, shows that the initial Inquirer story had been correct in this respect and that it hit a nerve very deep within Intel.

The P4EE is nothing more than a repackaged P4MP as can be proven from the CPUID of F25 (if you change the stepping, that is you change the electrical characteristics, the CPUID would have changed). What he is saying is that it took a lot of work to get the P4MP process up to the point it would run as fast as a normal Northwood and do so on a 800 MHz bus. Note that these are all process and packaging changes, Intel did not spend one cent on chip design here. Note also the arrogance and the totally disdain and disregard for the P4MP customer, Intel had no intention of spending ANY real bucks making that chip better since they own that market right now and their "manhood" is not at risk by being shown up by AMD as it was with the consumer marketplace.

As it is the P4EE is still getting better and faster chips than you can get as a P4MP or a P4DP. We grant you it takes time to get any chip ready for release but it did not take more than 6 months from time of initial proposal to customer ship on this chip which is extremely quick as it is and probably took less than that.

In "Pentium 4 overkill - trio of chips compared", it is too bad that Anand did not do some more low level benchmarks as opposed to application benchmarks because his overall statement that the Prescott scales better than the Northwood is unjustified without it. What he really proved was at 3.2 GHz the Northwood design, even when coupled with the latest in memory technology, is really cache starved (or memory stalled, take your pick) and the L1 D cache and L2 caches on the Prescott being larger have alleviated a lot of this (this has always been one of my big complaints about the Pentium 4 multiprocessor design, the L3 cache is so far removed from the processor core that its effectiveness is greatly compromised and that since the P4 cache is an inclusive cache the effect is even worse).

In "Intel Prescott sizzles to 77° Celsius" the section on X-Bit labs is important -
http://www.xbitlabs.com/news/cpu/display/20040212193648.html

This article is undoubtedly true and confirms the Prescott slip is now up to 6 months. What is important to note is that this is a ELECTRICAL change not just a process one. The chip has been redesigned for the fourth time which shows how much trouble they are in. But I would bet that the fourth time is a charm, at least as far as getting the temperature down. I am inclined to believe the rumors that Intel has imported people and technology from the Banias group to teach them how to make fast processors that don't double as egg fryers. What this does tell us is that the Nocona dates are now fiction, three months after they were definite. Earliest Intel could release Nocona now would be August (they would have to be suicidal to release it based on the C0 stepping since they would have to turn around and do it again when D0 is available which means that they will recharacterize and release on the D0 stepping three months after the May 7th D0 stepping launch). What will be really interesting to watch is that since the heat is off (they released Prescott and there is a 3.4 GHz chip, ignoring the fact that it is not a Prescott) will they let the 3.4 GHz Prescott slip from March to May and release it as the first D0 chip instead of continuing to fight to make the Prescott work at 3.4 GHz as a C0. What this article really proves is that Intel HAD to release a 3.4 GHz by Feb 15 (or else lose a LOT of money) and that the Prescott launch was a paper launch to stop the clock and save them from embarrassment rather than being the real product which we will see on May 7th.

T

Subject: Re: Intel Pentium 4 spanks Apple Mac G5
"Just think what might have happened if there were dual Pentium M machines."
Not much, except the PC wouldn't have been burning 400W of power.

Just because the P-M is substantially more capable than the P4-M doesn't mean that a pair of perhaps 1.8ghz modified P3s would spank a dual PPC970 box. For one, the bus bandwidth on the P-M sucks, in comparison to either desktop P4s or the 970, which severely limits its scalability. Furthermore, Intel's inability to ramp more than 100mhz up from the 1.6ghz launch clock after more than 9 months on the market as their "high end" mobile part would seem to indicate that the chip doesn't scale terribly well on the clock front. This shouldn't be surprising, as it wasn't meant to, and as it's based on a *power-* (not clock-) optimized version of a very old core that you may recall had terrible times creeping up much past 1ghz. But it does mean that you can't assume desktop versions of these chips could instantly be 35% faster than their existing mobile counterparts, just as the desktop P4 runs up to that much faster than the P4-M.

Maybe you guys were joking, but in all seriousness, such a box could provide a decently fast dual-processor setup for very compact and low-power/heat applications -- but then again, so could dual PPC970FX's at 2ghz/25W, and they don't suffer from either an inability to scale in clock rate nor a painfully low bandwidth shared bus.

It's been a while since my days as a Mac-head, but I'm starting to believe that IBM actually has a good chance of having the fastest desktop processor on the market by year's end, in spite of the so-so launch speeds of the original G5 and its relative age on the market by now.

Peace out, and may the Centrino be with us all,
Jonathan

Subject: Re: 90nm process
I have been following the progress of Intel's 90nm process development as reported in the Inquirer, and I would like to comment on some of the qualitative aspects of the development of 90nm (and smaller) CMOS processes for silicon transistors and the competitive demands of the marketplace.

Any structural component (gate, source, drain, interconnect, dielectric, etc.) in an integrated circuit or individual transistor is a three-dimensional object that typically has at least one solid interface with another object. This interface may be characterized as a change in dopant level within a continuous crystal lattice, or it may comprise a change to a different material having a different lattice (or amorphous) structure. In either case, there are thermodynamic forces (e.g., entropy considerations) that act to modify the nature of the as fabricated solid interfaces in a device. Considering that a silicon atom is nominally .235nm in diameter and 90nm is about 400 atoms, atoms at interfaces do not have to move very far to produce a change. It should be noted that gate dielectric thicknesses are on the order of tens of atoms.

For larger scale devices, the fraction of the component volume that is susceptible to changes due to interfacial influences is relatively small, and diffusion over a given time at a given temperature will not appreciably alter the performance characteristics of the component. However, as component dimensions shrink, the interfacial regions comprise a larger fraction of the component volume, and changes within the interfacial region will produce a greater change in the component performance. Scientists and process engineers are well aware of this on a qualitative level, but I wonder whether the potential impact on integrated circuit performance has been quantified sufficiently.

Accurate modeling of the interfacial changes in an integrated circuit must account for the effects of time, temperature, electric fields, and electromigration. Well known bulk material properties are of little use for modeling. Diffusion parameters and lattice strain behavior for interfacial regions are not easily obtained. Again, the technical people involved are aware of the difficulty in deriving accurate behavioral models. I can remember when electromigration in aluminum bond wires caught people by surprise.

In my own experience as an engineer, I have found that marketing and management often do not like to hear about vague potential future difficulties in a product, but they are more comfortable with vague potential problems than concrete future problems. When a technical person proposes an approach to define a potential problem through extensive modeling or empirical studies, management will often prefer no answer to the risk of getting an undesirable one. There is also the understandable opposition to diverting resources from product development to research that is not enabling for the product.

As far as microprocessors go, the ability for a processor to reduce its operating clock frequency and/or voltage is a built-in mechanism for allowing the processor to adapt to the degradation of the device that occurs due to interfacial changes. Such processors will not suddenly fail, but their performance will gradually decrease. Due to the exponential nature of diffusion related processes, interpolation or extrapolation of accelerated life testing is not always reliable. In an industry where product development cycles are typically shorter than the expected product lifetime, true life testing is impractical.

When one considers that in the real world product development may not be delayed in order to incorporate a demonstrated improvement, it is not surprising that it will not be delayed to undertake an extended search for potential problems. About twenty years ago I was working on microwave integrated circuits for the AMRAAM missile. For aircraft carrier deployment it is necessary to protect the missile's radar system from the aircraft carrier's radar since a carrier radar pulse could destroy the front end of the missile's receiver. I undertook the task of developing a thermal model for front end limiter PIN diodes based upon the waveform of the carrier radar pulse. I discovered that by increasing the thickness of the gold bonding pad, a diode's resistance to the carrier radar waveform could be improved considerably. The model was corroborated by having a skilled assembler use a wire bonder to "mash" additional gold on a diode prior to conventional assembly for test. The modified diode was able to withstand a pulse power that was more than 50% greater than previously seen. I proposed that the diode manufacturer be contacted so that additional gold could be added at the wafer level, but I was told that there was simply too much effort required to effect the change in the program.

After reading about 90nm process difficulties, I have to wonder about how robust 90nm processors will be and whether they will be immune to observable performance degradation during their operational lifetime. It would only get worse at 65nm and below. Given the competitive nature of the business, I think that the players will adopt the philosophy that it is easier to get forgiveness than permission. I am not very well informed with respect to current microprocessor processor development activities, so these comments are speculation.

Regards,
Dean

Pentium 4 VS G5
The rest of the story behind the Pentium 4 VS G5 shootout that you reported on was thankfully told by Rob Galbraith's site, since your site chose not to print it. While I'm not a professional photographer and have no problem thinking that Galbraith's report is likely accurate, Rob Galbraith, unlike the Inquirer, was able to succinctly put this year's shoot out into context in that Apple has significantly progressed in closing the performance gap in a mere 12 months while the PC world has progressed at a slower rate. It's worth at least one sentence in your article to mention that, isn't it, since Galbraith spent several paragraphs resulting in a good portion of both the intro and conclusion of his huge report in order to put the Xeon win into context? I doubt it was purposeful of you to leave it out, but perhaps instead the reason was more sloppy reporting than Galbraith's reporting? The performance gain is a huge accomplishment of Apple and IBM in competition against Microsoft and Chip-zilla, and here are Galbraith's words which provided the context:

It's now a year later, and a lot has changed in the Mac world: Apple has moved its Power Mac desktop line to the G5, a much more powerful processor than the one it replaces. The company has also released OS X 10.3, a sweeping revision to the operating system driving modern computers from Apple. It has been 12 months of solid progress for the Mac folks. (...)

By comparison, the mainstream PC's year was a little slower paced, at least when the measure is operating system revisions or processing horsepower increases that benefit pro digital photographers. Windows XP Home and Pro offered largely the same set of features in December 2003 as they did in January 2003. Similarly, the year began with the Pentium 4 processor ticking along at 3.06GHz, and it ended with the P4 only a hair quicker at 3.2GHz.

The geekiest among you will have noted that there were other speed-enhancing improvements in the architecture around the Intel processor, including a faster frontside bus, faster RAM and, in the Pentium 4 Extreme Edition, a larger L3 cache. Plus, dual processor Intel Xeon machines also reached the 3.2GHz mark, the speedy yet power-efficient Pentium M processor for laptops was released and AMD began to deliver its 64-bit Athlon processor lines.

This flurry of activity, however, added up to only small performance gains for pro digital photography tasks, at least when measured against the heady performance bump on the Mac side. In fact, the combination of a big leap forward in processing power on the Mac desktop, the emergence of RAW file processing software better tuned for the Mac architecture and relatively modest horsepower increases for the Windows crowd meant there was the real possibility that the Mac closed the performance gap last year.

(...)

For Mac users, this report is a lot less gloomy than the January 2003 version. The greater computational horsepower of the G5 Power Macs allows them to complete all of the tests in this report much faster than the G4 machines they replace.

Mac OS X 10.3 plays a role here too. For the first time since we began measuring card-to-computer transfer rates, the Mac is able to match or exceed the throughput of a computer running Windows. For years, the Mac operating system's ho-hum code for handling FAT-formatted removable media - including CompactFlash cards - has meant comparatively pokey transfer rates, even on the fastest Mac computers. The all-new FAT plumbing in OS X 10.3 finally puts an end to the slowness.

Software developers also appear to be heeding the call from Mac users for better RAW file processing performance on their chosen platform. For example, the Photoshop Camera Raw plug-in for Photoshop, C1 Pro and MacBibble all take advantage of the dual processors in Mac computers that are so-equipped. The result is processing times for MacBibble and Photoshop Camera Raw on the Mac that are competitive with a fast dual-processor PC. In fact, MacBibble handily outpaces Bibble for Windows in batch conversion of Nikon D1X NEFs.

John G