The Bristol-based firm claimed its CS301 design delivers 10 GFLOPS per watt, and that, it added, can make high performance computing (HPC) available and affordable.
The chip is likely to find applications in scientific, engineering, biological, and content creation, the firm said. It uses a multi threaded array processing archicture with 64 processing elements, 384K of SRAM on the chip, and IO ports that use its apparently proprietary bus.
The idea is that each processing element includes local memory, local floating point units, and IO.
The bus - dubbed Clear Connect - is a packet switched model.
The chip will act as a coprocessor for either AMD or Intel CPUs within blade servers, workstations or clusters.
There's no details as to when the chip might see the light of day. Clearspeed will also license the intellectual property of the chip, it appears. µ
See Also
Clearspeed gets 40Gbits/ps namechange
* Corrected