AMD talks up Barcelona power

AMD IS OPENING its kimono on a few more of Barcelona's features, and at the ISSCC chip confab it is talking power savings.

Barcelona has a lot new to offer on this front.

The first thing that Barcelona adds is a very much more flexible clocking scheme for the cores. There are PLLs for each core now, so they can be clocked independently. With the older K8 chips, all cores had to go up or down together regardless of load.

With Barcelona/K10, each core can change speed as needed potentially saving a lot of power. The only problem is that they can not vary voltage independently on each core so more power is consumed than necessary. Put this down for a future to do list. The voltage is set by the most loaded core, so it can ramp down quite a bit on really light loads.

More interesting is the memory controller power savings. New to K10 is the ability to manage DDR channel power. If K10 sees that memory is using only writes, it can shut down read channels. If it is only reading, it can shut down write channels. This again saves a chunk of wattage.

On a more micro scale, AMD has stepped aboard the fine clock gating train. Coarse grained gating is shutting down large blocks of transistors to save power, and fine grained is shutting down much smaller numbers of transistors. K10 gets, according to AMD, 'really aggressive' on the fine grained clock gating, and improves coarse grained a bit too. It all adds up to more saved watts.

The last part is new Powernow modes - most importantly the ability to not use drivers. Current K8 chips all need a driver to use anything but the bare minimum of Powernow modes. K10 catches them up to the Intel cores in being able to operate independently of the OS, it just works.

The three things that AMD is doing to save power are all additive, so the net power gains should be fairly large. If you look at the projected power numbers for the chip, it looks like it hit the mark. µ