The Quick INQ guide to designing chips

THIS IS not meant to be an in depth article covering every minute aspect of chip design, but it is meant to take away some of the mystery of what happens between a thought entering an engineer's head to a design being produced in silicon for the first time. Since I am most familiar with the graphics market, I will cover their little design strategies. While other chips may have a slightly different design methodology, from 10,000 feet up, they generally look the same, except in the fine details.

The engineers take the idea and create design flows of how the hardware should work. This includes logic, registers, cache, and data flow pathways. Once this high level work is done, it is time to start laying out the design. There are two basic ways of doing this; engineers take months and years to carefully hand layout the transistors in custom cells, or they can use higher level EDA (electronic design automation) to quickly lay out a design. The software comes from guys like Cadence, Synopsis, Mentor Graphics, etc.

Hand layouts and custom cell design are incredibly time consuming, and it can take a skilled engineer a month to do a small, custom PLL by hand. While it may seem somewhat backwards to go this route instead of having EDA software do it for you, there are great advantages to custom cell design. The biggest advantage is that the electrical characteristics of a custom cell are very well known, and the switching speed of custom cells is four to six times faster than a standard (automated) cell. CPUs that run in the GHz realm are mostly custom cells. The disadvantages of custom cells are the time involved in laying them out, as well as the non-standard size and shape of the custom cells. Now, there is a lot of re-use between designs, not to mention massively repeatable logic like caches. So designing a CPU is still a long and manpower intensive operation, but they have tools and know-how to help get around most of the big show-stopping problems.

Standard cells are not nearly as fast as custom cells, but the regular shape of them makes it relatively easy to put a complex design together. Much as building with blocks, using EDA software a basic ASIC design can be brought up fairly quickly and oftentimes will work quite nicely right out of the design process. With more complex designs, this is not always the case, as a lot of verification has to be done to make sure all the components work as they should - think NVIDIA's video accelerator in the NV40. The advantage of the standard cell is the repeatability of the design, and the ease of integration using automated software to place and route. The primary disadvantages are lower speed and higher power consumption compared to custom cells. Fabs such as TSMC and UMC have their own standard cell design depending on which process is being used. A standard cell on TSMC's 90 nm is not the same as a cell from UMC's 90 nm process due to the electrical differences between the processes. If a finished design is ported over to a competitor's process, then the product needs to essentially be redesigned with these new cells, and the verification process must begin again.

A third option, and one that is used quite a bit more often these days, is Dynamic Logic. The idea behind Dynamic Logic has been around for quite some time, but it was typically slower and more power hungry than other options. DL has come a long way, and the advantages of such logic in current designs often overcome its drawbacks. The DL option that has been talked about extensively is that of a little company called Intrinisity. This company promises near custom cell performance while still being able to use automation to quickly bring a design to production, yet still allow greater power savings and higher clockspeeds than by using standard cells with static logic. So far Nvidia and ATI have both invested in the technology, but we have yet to see anything concrete beyond press releases.

Current GPU designs often have a mix of custom, standard, and dynamic logic. As designs progress, software improves, and functional unit re-use becomes more common. This allows more custom work to be done, because the time and money spent on that work can be taken and used in future products.

Once the design has been generated it must go through a long and thorough verification process. This is done through both software and hardware emulation. Software emulation virtualises the design and tests for functionality, timing, and other basic electrical properties. This is done on server farms, and is very time and computing intensive. Hardware emulation is done by large and expensive FPGA boxes that can be programmed to emulate a complex design. These boxes run at KHz speeds vs. MHz when emulating a chip design, but they run significantly faster than software emulation and can often pick up errors that software may miss. Companies such as Mentor Graphics - which merged with IKOS - and Tharas provide full systems for hardware verification.

Once verification is complete and the design is signed off, the chip layout is done using CAD or other software, and those results written to GDSII or OASIS format. This data is then put to media to be sent to the photomask writer. This time is commonly referred to as "Tape Out". The origins of that name go back to when data was written to magnetic tape and sent out to have the photomasks produced. Photomasks can be very expensive, and in complex designs can reach upwards of $1.5 million US a set. Companies such as ATI and Nvidia want to make sure their designs are solid before ordering masks, as small mistakes could require new masks to be produced.

Getting back first silicon is incredibly important, and these companies will pay a lot of money to get the results sooner rather than later. The average wafer typically costs around $1,500 to produce from start to finish, and more complex designs using the most advanced process can see prices as high as $6,000. The production time for such wafers can reach upwards of 3+ months. This is unacceptable for first silicon, so these companies pay extra to fast track these initial wafers. This brings the cost of each wafer anywhere from $20,000 to $100,000, depending on the speed and process desired. Fast tracking a wafer can have finished product in a customer's hands in about four weeks.

Once first silicon is in hand, then the engineers can work on what changes need to be made to both the basic design and the metal layers. First silicon performance and functionality will then give a good idea of when a product's design can be finalized and full-scale production can begin. If the first silicon is good enough, that design may in fact go into full production. If small changes are made then a new revision can be brought up within several weeks. In the worst case scenario it could be six or more months from first silicon to a final production design - think ATI's R520.

This of course is a very general overview of the process, and there are many minor stages left out, such as focused ion beam diagnosis and repairs. But hopefully this will give a better view of some of the complexities and costs of designing an ASIC. µ