Intel's 90 nano technology to use strained silicon

We know that Intel has planned to move from its current 130 nanometer to 90 nanometers for some time, but Barrett will describe a process called "strained silicon" which is already used by IBM.

Strained silicon will increase the speed of transistors, while copper interconnect technology, which competitor AMD has used for some time, also increases performance.

The firm claimed that it used a 90 nano process to make SRAM chips at 52 megabits last February, with around 300 million transistors in a 109 square millimetre area. The SRAM cell size is one square micron, claims Intel, which is 100 times smaller than a red blood cell. This SRAM technology will help inprove cache sizes in the future chips.

Prescott and Nocona will include seven layers of copper interconnect using 248 nanometer and 93 nanometer wavelength lithography, and Chipzilla reckons it will be able to reuse 75 per cent of the process tools on the 12-inch version of its 130 nanometer technology for the new process.

What does all that mean? It means Intel won't have to spend quite as much of the $9 billion cash it's got in the bank as it usually does, when it moves to new processes.

Manufacture of these chips will start in the D1C fab move to other 12-inch fabs next year, and Intel claims it will have three such fabs in production at some time during 2003.

When Intel starts producing its Prescott and Nocona processors next year, they will use this technology. Chips are expected to start appearing in the second half of the year, as revealed here, but it will take some time for the chip giant to transfer the process to other than a few fabrication plants at first.

The firm will claim that transistors used in the 90 nano process will be the smallest and the best performing CMOS trannies in production, using gate oxides five atomic layers thick.