AMD roadmaps: fast horses ahead

Sure enough, it was - zut alors - very interesting indeed.

The document outlined AMD's cunning market strategy in the desktop, mobile and server space and show that AMD won't just stick with those but get into IA (information access) devices too.

Its plans are modest, but cunning. It wants to expand its current position in the consumer and small/medium biz desktop markets with the XP and promote Socket A to grow its admittedly modest share in government, education and enterprise.

It will carry on selling the Athlon 4 mobile processors and position the Athlon MP as a high performance and scalable chip for workstations and servers.

We know what its aim is with X86-64 and Hammer, and that's to give better performance on 32-bit apps and sneak in to 64-bit computing that way.

AMD will use Socket A for the whole of this year and next and claims that over 50 vendors with more than 300 Socket A mobos are out there in the wild.

The roadmap made the fair point that Intel's socket plans are highly confusing, and this diagram demonstrates that better than anything else.

AMD psotions the Athlon as the "world's leading X86 chip" while Durons are for "everyday" computing for biz and home.

It also claims that Windows XP goes a long way to use AMD's CPU optimisations, including 3DNow! Prof, DirectX 8, PowerNow - with native support, MP and 760, and that Windows XP recognises system level instructions such as SYSENTER, SYSEXIT, CMPXCHG8B and Conditional Move. This somehow implies that maybe the Pentium 4 doesn't - anyone help us out on this.

As we reported last week, .13 micron Thoroughbred Athlons will use the Palomino core and Socket A and is scheduled for Q2, while the Appaloosa Duron will only have a front side bus of 266MHz, will use PR rating, and is also scheduled for Q2.

In an update to the roadmap, we learn Barton at .13 micron SOI is scheduled for the second half, Clawhammer at .13 micron SOI does indeed move into Q4, Sledgehammer MP for the first half of 2003 along with Clawhammer DP. But at the back end of the first half of 2003, AMD will start experimenting with .09 micron Clawhammers.

Thoroughbred comes with 384K cache, a 266MHz FSB, .13 micron technology and it's already sampling. Appaloose has 192K cache, 266MHz FSB, is also .13 micron and samples later this half. Both support 3DNow Professional.

Barton also has 266MHz FSB, uses .13 micron SOI, supports 3DNow! Pro and AMD will sample it "as the market requires" - interesting phrase that.

ClawHammer samples the first half of this year at .13 micron SOI and is designed for 1/2 way multiprocessing machines. Production is slated for the second half of this year while it will sample during the first half of this year.

The .09 micron Clawhammer will have a 64 square millimeter die, while the same Thoroughbred-S will have a 50-square millimeter die - comparing to an 80 square millimeter die when Intel brings out its .09 micron technology, Northwood-S.

There are a few differences in launch dates compared to those we published earlier in the week.

In Q2 we'll see the 2200+ Thoroughbred and the 2000+ Thoroughbred, the latter edging out the 2000+ on the older technology.

In Q3 now we'll see the 2600+, the 2400+, the 2200+ and the 2000+, all using Thoroughbred cores and a 266MHz front side bus.

At that time we'll also see the 1800+ Duron using Appaloosa technology.

So the Duron will move to 266MHz front side bus in the middle of this year. DDR (double data rate) memory is in AMD's words "now ubiquitous" and system integrators can use SDRAM PC-133 for lower price points.

So the 2600+, 2400+, 2200+ and the 2000+ at .13 micron will have a core voltage of 1.60 volts, use a maximum power of less than 72 watts, and all will use the famous "organic package" we spoke of before.

On the chipset side, the roadmap Fred showed me matches others we've seen, and of course it has its own, ALI, Via, Nvidia, and SIS to support it.

AMD reckons its T-Die (higher maximum allowable die temperature) means that Intel has to build more expensive fans, coolers and other elements into PC designs, while it is using a low cost model which means designs are easier.

AMD warns that changes for Thoroughbred, given Palomino as the starting point, mean system integrators should be aware the CPUID will be 680h, voltage 1.60V, and PowerNow frequency switching may be turned on. Passive components will now go back on the top of the CPU package.

AMD wil bung Hammer into enterprise servers with large on die caches aimed at 4 and 8 way MP systems, mainstream servers and workstations using one and two way systems, performance desktops, and performance notebooks using very low power.

More on all this later. µ