Intel's hidden Xeon, Pentium 4 bugs

First I refer to your own article, "P4 2.80GHz Bapcocked to 3.917GHz".

Mike Magee originally alerted me to the cache problem with the Xeon P4 MP on May 28th this year.

There are two significant bugs in the L2 cache of the P4 which may have required Intel to do something on the order of modifying the microcode to cause hardware prefetch to have to be turned off.

We know definitely that the similar bug in the Xeon P4 MP does require you to disable prefetch and thus take the performance hit. Checking the new errata for the "new c1 stepping" update we find Intel has finally fixed these problems and thus these may be the source of the amazing increase in performance.

If so, Intel is not advertising this fact as it would lead to embarrassing questions about how they have flogged partially inoperative P4's for the last year or so.

Relevant information
Errata N53 and N62 have finally been fixed clearing all known cache problems with these processors and thus allowing Intel to remove internal workarounds they have introduced to obviate these problems (N62 being the more important).

Specification update is at this Intel FTP page.

Originally Dave Jones points us to the bug and Codemonkey. See Friday, 24th, errata.

The relevant doc is this Intel PDF.

See item O37. The fix for the bug (disable hardware prefetch) means a loss of performance. In some applications a significant loss.

After further readings and comparisons of the three P4 errata (P4, Xeon P4 DP, Xeon P4 MP) the following has been determined.

The cache/prefetch problem exists on all three processors but on the non-MP versions the problem is between level 1 cache and level 2 cache whereas the MP version is on Level 2 and level 3 cache. The effect is much worse at the L3 cache level then it is at the L2 cache level (probably due to the second cache controller). All problems seem to be related in that they were all discovered at approximately the same time (as determined by the order of other common problems to all three chip types).

On an MP you must disable prefetch. On the others, Intel weasel words you with "the problem can be handled in the BIOS" and "This condition has never been replicated in commercial software". Since that little piece of code that Intel supplies tells the BIOS how to set up the CPU for each stepping, no one but Intel has a clue what is being enabled/disabled (note that hyperthreading, although present in the B0 step, is disabled in the BIOS until new BIOS's which support C1 stepping are distributed).

N.B. that this type of code disabled a major part of the original Pentium processor because the optimizations didn't work right.

I admit if you read the Intel description this is pretty innocuous and should cause no problems for anyone but my rather jaded self is bothered by a performance increase where there shouldn't be one and fixed errata are the first place you go looking. Given that and Intel's ability to micro manipulate the processor without anyone knowing and thus are born conspiracy theories.

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