The articles appear to be based on two separate steppings of Prescott CPUs. The notes on the compterdiy site indicate that the new Pentium 4 core (Prescott), may be running 14 per cent slower than the older core (Northwood), indicating that it could have between six and eight extra pipeline stage. Each stage could gobble up about two per cent of performance.
The hardware juries, when their NDAs expire very soon now, will find it hard to tell exactly what's happening because of other features in Prescotts that speed up performance.
The other comparison - at pconline - appears to be a different, later, stepping and appears to show that in this stepping the Prescott is between two and five per cent faster that the earlier one. Intel may have re-ordered execution sequence to improve the timings.
The interesting thing with this later stepping, if the site indeed has Prescott samples, is that the ALU (arithmetical logic unit) isn't double clocked anymore, demonstrated by the drop in Dhrystone numbers compare to the Whetsone ones.
In the Prescott's favour is that the increased caches and branch prediction turn the pipeline losses into a 35% performance improvement. If the numbers are to be believed, 20% of that is because the L1 D cache has risen from 8K to 16K.
We know that Intel has managed to include strained silicon into the Prescott, but the chip firm is still fighting shy of silicon on insulator (SOI). In public, Intel execs say it's untested, tricky to implement and the like.
But in private there's likely to be another reason for its reluctance to introduce SOI. Many of the SOI patents are owned by Big Blue, which prefers to trade tech rather than license tech to others.
If IBM insisted on a trade, Intel might have to face a horrible taste in its mouth by giving away its "IP crown jewels", maybe including its "Dothan" technology for the SOI tech Big Blue has.
As IBM Microelectronics appears to be doing a roaring trade right now in the foundry business, presumably part of the trade would be that Big Blue didn't manufacture Pentium Ms and Prescotts for themselves, but the support chips would compromise INTC's lucrative chipset business.
As for future 65 nano tech, Merom/Gilo is a completely new processor it now appears, with Tejas and Jonah becoming just souped up Prescotts and Dothans.
Intel desperately needs a new chip architecture and if this technology has started, then it suggests that the promotion of the Centrino boys the INQUIRER covered last week may indeed mean more than it seems.
A multiple core, independently schedulable chip with sub processors might just be the ticket for 2005/2006.
Indeed, INTC seems to have put itself in a place it doesn't really want to be.
It could use a better high-k dielectric just coming to market and metal gate technology which Intel could bang in there as a quick fix - although the question of IBM patents rears its head here as well.
Or it might decide to pull in multiple gate mosfets, which are at least two quarters away from reality. For reality, read production.
But the future is grim too. The chemistry INTC uses starts to fall apart at 45 nanometres, while the IBM-AMD excess of weevils collapses at 32 nanometres.
Intel might have had an opportunity to double the size of L1 I cache in Mr Prescott, but the trouble is the chip just ain't designed that way.
We'll be interested to see how the spinners play this one at the launch of the Prescott processors. We've already reported on the weird benchmarks they've been showing hacks everywhere. µ
Intel Prescott benchmarked against Northwood 2.8GHz
2.8GHz Prescott benchmarks, ATI PCI Express bubble on to web
Intel's 65 nano Jonah jinxed?
Intel's Prescott edges closer to 100 watts
Prescott delay avoids Intel launching toaster, rather than chip
Intel in apparent disarray over launch of Prescott chip
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