Get back in your shell, you cirriped
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Flash new standard tips up
INTEL, Microsoft and Dell have signed off a new spec for the use of NAND flash in PC applications including hard-disk caching and solid-state drives.
The Intel-led NVMHCI (Non-Volatile Memory Host Controller Interface) Working group includes more than 35 members and its new NVMHCI 1.0 spec outlines the hardware interface and command set.
"Several NAND solutions are coming on the scene to take advantage of the ReadyBoost and ReadyDrive features of Windows Vista," says Bob Rinne, general manager of Windows Hardware Ecosystem at Microsoft.
"Standardising on a common controller interface will enable more integrated operating system support of these solutions moving forward."
The spec describes an interface that uses only eight commands, allowing the memory controller to optimise for both performance and endurance, and is designed to enable caching of hard-drive contents into non-volatile memory by a single driver. µ
L'Inqs
NVMHCI
Full spec (PDF)
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It is quite fun to see non volatile memory being used for adding "RAM" to the system .. it's good to know that if I find some company that is willing to go Vista, I can just take a walk down their work booths, nick the boost key and get their passwords (well, something at least) from the RAM that is stored on non volatile memory .. meaning I can board the train, take the international flight, nap, get some beer at the pub, sleep the alcohol off, then be ready to access the "RAM" of a machine I took some days ago.. (volatile memory at least has the decency to fade away in a moments while)

Its perfect :)
Physician Thomas Drashek M.D. 
Please stand up!
comment two is correct, yet AHCI is Advanced Host Controller Interface mentioned, which if used in Pci configuration takes precedent over 32 bit standard or 2 16 bit dwords. D stands for Data. With pci/Pcie standard lower 32 bit word(Bar0) & upper 32 bit word(Bar1) are used, so Above 4 gb limit, NOW Sky for Ultie Limit.
Commands:Plenty O'Them listed, RUINING My Ultie Command Hullucinations by already existing standards=, Guess thats what Standards are for.
here it is in print:07 RO 1 64 Bit Address Capable (C64): Specifies whether capable of generating 64-bit
messages. NVMHCI controllers shall be 64-bit capable
Man I could have told you that in million years.
If you want Pci-X, O.K. go figure.However:Register accesses shall have a maximum size of 64-bits; 64-bit access shall not cross an 8-byte
alignment boundary
Yeah, You Know it. Each command line of 32+ goes then to command table so although specification allows more than 64 bit, it is unlikely, unless your TimeTraveler.Hehe.Because each command table is linked :This address shall be aligned to a 128-byte address, indicated blah,blah,Woof,Woof. So expanding basic instruction sets is almost infinite or therefore REWRITEABLE AS INSTRUCTIONS ARE CREATED & TESTED. Glad arn't YE. Well look glum, upper 32 bit case is completely labeled RESERVED, Meaning Go Out & Write It. Do Dah, Do Dah. CAMPTOWN RACES DANCE & SING.
fLUSHING OF vOLITILE TO nON vOLITLE IS TO BE WRITTEN, each sector can be 512 to 8 kb, with 4 kb written is standard? To Date. Meaning all 8 kb work, yet parmeters from 4kb to 8kb are RESERVED. MB Burst may reach 60 mb/sec, just nOT Enought to Load O/S from Home is: Ultie Mfg. Guess.
So Ultie must invent one: AT/ first figure out bits 33 thru 64 then report back. Next, Ultie lie dynamic host controller over 4 parrallel units as AT completes job, in fact make that 8 units. Use EFI admendium to 16 bits.hahaHugh? Then Ultie_3.0 Copyright: ULTIE_TOM PAT.PEND.
Well thats basic idea. Final burst speeds approaching 480/960 mb/sec, if you can handle inventive sort of Hardware design. Right now figure 30 mb/sec done, 30 mb/sec being added to, thats it, Chief.Didn't I already Know that?Bet Your Mansion On BOBTAIL Grey,Boohoowho.
T. Stewie Drashek

AT:ADDS Can it be written in Portugese?
Here with DMA standard included 66 mhz/s is Fresh Start, yet between inevitable increase in speed, Even for:Ultie_Toms' Propalene Lifestyle, only 8 Commands is THIN.

Shirley 1.0 is going to improve to larger instruction set, might not larger, that is Rewritable, controller be possible, with say Much,Much more So Ultie Games can go, oh, 600 mb/s? How? Eliminate redunduncy. Instead of using same memory shod in 8 places to pour it out, just use one & repeat it 8 times:At Same Time, Wow, What are You Thinking? 
Well who knows what might be needed, it is NON Volitle, meaning its lasts long time between useages, No Recharge needed. Brains, what where YOU Thinking.

So far, to page 11 thats what i've seen, that instructions are going to go beyond 8 to say 16 or 16 twice or even add 16 more i nsome cases. Yet you'll need New, New standard, Ultie 3.0, or something.When whole system gets caught up.
Anyway it looks great & slow, just ulties thinger. At least it should be out soon enough: now?
133 mhz/s dma might just hold O/S, yet NOT so sure about install. See, Two controller inst. of 8 for 266 mhz/s or 32 inst for 512 mb/sec?, NOW thats Ultie 1.02
LETS SEE PRODUCT, MAC.
T. drashek



I used DMA in its Pci (optional to isa 35 bit or less, standard & optional to 1.0 here)content, Double Address Cycle. Being 64 bit or more to address more than 4 gb memory, its probable that will be needed for SSD.
Also DMA for starters skips CPU entirely & routes Data/Job about without CPU lag.c In Effect DMA can be located in any controller & acts like little PU.Imagine SSD with BUNCH O' SEPERATE CPU's INSIDE, EACH WITH OWN O/S. instant on/off of any O/S you'd like.
This brings up Concept of APIC or Advanced Interupt Programable Controller, where you could have up to 60 PU in system, allowing Multi Processing. Word: Programable & Option: Rewriteable, are about Same From Ultie_Tom at this poiint.
Again, Probably more instructions would be fitting Such Beastie.
Well, got to go read more pages, just thought clear up p.1-11, so far.First Snag Hanger is isa DMA until 64 bit width standard(called Pci), being unable to address more than 4 gb memory.?Pages 13-32 coming up NEXT.
Thomas Drashek