Open source SPARC details emerge

This comes several months after the original release of the source code for the design of the '64-bit, 32-threaded' processor, at the end of March.

A 240-page pdf here, and contains 'detailed functional descriptions of the processor components, and the description of the architecture of each component of the OpenSPARC T1 processor, including detailed block diagrams and signal list for each component'.

It's an interesting chip, and due to the GNU GPL open-source license it's released under, will soon be embedded into university lectures for beer-swilling tax-evaders world wide. Here's a quick synopsis of the OpenSPARC T1's features:

• 8 SPARC V9 CPU cores, with 4 threads per core, for a total of 32 threads
• 132 GB/sec crossbar interconnect for on-chip communication
• 16 KB of primary (Level 1) instruction cache per CPU core
• 8 KB of primary (Level 1) data cache per CPU core
• 3 MB of secondary (Level 2) cache - 4 way banked, 12 way associative shared by all CPU cores
• 4 DDR-II DRAM controllers - 144-bit interface per channel, 25 GB/sec peak total bandwidth
• IEEE 754 compliant floating-point unit (FPU), shared by all CPU cores
• J-Bus interface (JBI) for I/O - 2.56 GB/sec peak bandwidth, 128-bit multiplexed address/data bus