When you have to kill a man, it costs nothing to be polite - Winston Churchill
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Tukwila, Silverthorne and MLC flash tip up at ISSCC
INTEL PUT OUT a blizzard of papers for ISSCC, and there are some goodies in there. The problem is that ISSCC is a conference about circuits, not chips, so don't expect much in the way of purchasable parts, just design info.
The biggest one is Tukwila, the latest Itanium CPU. Everything we hear about this project is that it is in great shape now and should be out later this year. The six bullet points that Intel put out are pretty sparse, up to 2GHz, four cores, two threads per core, and 30M of cache. It will have CSI (I can't bring myself to call it Quickpa....hack, spit) and a bit over 2 billion transistors.
The chip is aimed at large machines, no, not the XBox 1, there are bigger boxes out there, and they demand reliability, so Intel is doing that. This chips is designed to make errors hard to come by, detectable, and hopefully correctable, barring that, compartmentalizable.
Things get a little grey when they talk performance. Intel is promoting > 2x Montvale performance, not exactly a high bar to shoot for when you have 2x the cores, >2x the cache and a slightly higher clock. Toss in that they are measuring it with TPC-C, SpecIntRate and SpecFPRate, and 2x is pretty much a slam dunk.
Add in that the power went up 25 per cent despite a process shrink, 90nm - > 65, and we are not impressed all that much. Basically, the 2.5GHz part is now 2.0, but the 2.0 is pretty darn OK, all told.
The next big one is Silverthrone, a 2W max CPU that will require a completely different article to tell you about, look for it soon, but look for the full paper at ISSCC.
Another one Intel is talking but not talking about is Multi-Level Phase Change memory, basically a flash cell with four states, aka two bits. We are not sure what is more impressive, the fact that Intel completely skipped three-state flash, or that they won't tell you any of the product details, see the disclaimer about ISSCC above.
In any case, there are four states that any chemistry student would recognise, very amorphous, amorphous, semi-crystalline and crystalline. Intel uses an advanced algorithm to read the state, it is not on/off like the old days, but shades of on/off.
The devices will be out from Intel and ST Microelectronics, if that venture doesn't fall victim to the capital market brouhaha, sometime later with yet to be released capacities at a yet to be released price. This probably explains our yet to be realized excitement over the yet to be released technology.
Moving on to silicon radios, Intel is talking about integrating more bands on the same chip. You got a taste of it in Beijing last year when they were talking antennas, now they are going the way of radios. The paper promises to have Wi-Fi/WiMax Radios soon, and adding WPAN tech 'later'. We can't wait for WPANs, talk about social viruses...
Those are just four of the 14 new papers, and one recycled. The other cover 65nm digital amps, high density 2T memory, Spectrum configurable WiMax Recievers, and a bunch of others. If you are into these topics enough to want more, go to the conference, you will probably enjoy it. One thing you can be sure of, there will be a lot of Intel people there. µ
Tags: Intel
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Dear Charlie

I see that you have corrected the article, it originally talked about two process shrinks. I still find it unaccurate. As you know Intel doubles everything (but the cache) on Tuwkila but adds IMC and CSI, so it doubles transistor count. and at the same clockspeed it manages to keep Tukwila in the same TDP of Montecito despite using more power hungry transistors (it changes the ratio of logic, comunication... versus cache). 

Thay also increase performance clearly when going to higher clockspeeds (25% more) but suffering the logical penalty on TDP (only 25%, less than I would have expected).

So maybe the article should say "Intel is promoting > 2x Montvale performance, not exactly a high bar to shoot for when you have 2x the cores, QUITE LESS THAN 2x the cache and THE SAME clock. " instead of "Intel is promoting > 2x Montvale performance, not exactly a high bar to shoot for when you have 2x the cores, >2x the cache and a slightly higher clock. "

It is also surprising that you fail to notice taht the amount of L3 cache goes from 24 MB to 30 MB (double would be approximately 48 MB)

Best regards