Intel Thurley has early CSI interconnect

THE FIRST Intel "platform" known as Thurley is set for a second half 2008 launch and like Stoutland comes with a memory controller integrated in the CPU - this time the Gainestown CPU.

The Thurley volume server "platform" will support 42 PCIe lanes, of which 36 are generation 2 and six generation one. On the memory front, it will support DDR3 800/1066/1333 speeds, with six channels - that is to say three channels for each Gainestown CPU, and a total memory capacity of 96GB.

On the storage front, Monsieur Thurley will support eight SAS/SATA 3Gb/s with hardware RAID 5 which is codenamed Sunrise Lake. It will also support six SATA-2 ports with RAID 5.

The Tylersburg-DP chipset will also support Dual GbE Zoar/Adorami, and 10GbE "Oplin". According to documents seen by the INQ, there will be separate links for CPU-CPU and CPU-IOH traffic, while some features such as TM1 and TM2, DBS and GV3 will be cannibalised from Stoakley.

It is also likely to include extended visualisation, release 3.0 of iAMT, and will come with additional instructions to improve text processing and string search.

Intel hopes to have it on the IT Straße in the second half of 2008, indicating work is fairly well advanced on the CSI front. µ