Shanghai available anytime now
IT LOOKS LIKE AMD is getting ready for the big one. The firm is preparing no less than nine of its new 45nm quad-core server chips – codenamed Shanghai – this very month.
Five two-way and four eight-way server systems have been tipped to tip by Digitimes. These CPUs have integrated dual ECC DDR2 memory controllers and 6MB of L2 cache bunged on.
The socket is – as far as we know –identical to the current generation of Opterons: Socket F (1207). Initial speeds will vary from 2.3GHz to 2.7GHz. The original Barcelona core started its life at 1.7GHz and crawled its way up to 2.5GHz April last.
But that’s not all. From February 2009 AMD will surge forward with five new low-power versions of the same processors (two 2-ways, three 8-ways) running at 55W. There will be also two additional high-performance CPUs (also 2-way and 8-way) putting out 105W.
Although it’s been pointed out by AMD beforehand, the Shanghai marchitecture is built to operate on a HyperTransport 3.1 bus, although for reasons that AMD is sure to explain later, the first parts will only be HT 1.0 enabled. Those HT3.1 parts will show up later, according to the site. µ
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Is there any AMD server chipset that support HT3? I believe this is the reason for the HT1 parts.
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I would imagine that the first parts are HT 1.0 because they'll have to move to a new socket or at least a new chipset for HT 3.0. The original Socket F spec dictates HT 1.0 support, so that's all these systems are going to have.
It's 6MB L3... not L2