How to mix DDR3 modules

DDR3 MEMORY is still very expensive, yet the most of it is only available right now in 2 x 1GB kits for a 2GB total capacity. This is not exactly enough for running, say, a resource-hog like Windoze Vista there.

Now, you've seen the new "rules" that the upcoming Intel X48 chipse - the first to officially support DDR3-1600 memory and FSB1600 - will impose. Once you get on to that memory speed, you can only use one DIMM per channel instead of the usual maximum two, being limited then to the above miserly 2GB - at least until 2 x 2GB DDR3 kits arrive.

So, if you want truly fast DDR3 memory in sync with an overclocked 1600++ FSB, you're limited to just two modules.

Is that rule really a limit? Well, if we look at super-duper reliability demands set by Intel for 'standardised' DDR3-1600 use, the electricals at these high signalling speeds could pose a problem.

Does the stuff still work if the 'rule' is broken? To check that out under potentially most unfavourable conditions, we decided to take in two different dual DIMM sets: one OCZ DDR3-1600 Z3 XMP (Intel Extreme Series) set with default CL8-8-8 latency, the other a new A-Data Vitesta X-Series DDR3-1900 CL9 (non XMP) set, and replace the current SuperTalent ProjectX module set inside - it is going into the X48's instead.

They both went into the freeze chilled Vapochill test system using a 4.5GHz FSB1800 Intel QX9770 quad core Yorkfield, and Asus Maximus Extreme board with the most recent BIOS 803, running WinXP 64-bit with Sandra XII SP1 benchmarks.

The OCZ DIMMs sat in the first slot of each channel, while the A-Data ones were in the second slot round. By the way, both of these are, on their own, comfortably running DDR3-1800 CL7-6-6 T1 on this board at 1.9 volts.

We kept the DRAM voltage a notch higher than usual, at 1.96 volts instead of 1.92 v, and changed command rate to T2 instead of T1. We also had to adjust the AI clock twisting to Strong, and DRAM Channel 2 clock skew to be 50 ps - yes, picoseconds - ahead of Channel 1 to compensate for the 8 mm greater trace distance.

This working 4-DIMM setup resulted in around five per cent bandwidth benchmark performance loss in Sandra XII, from 10.4 GB/s to 9.9 GB/s and eight per cent higher latency, from 50ns to 54ns, compared to the 2-DIMM, one DIMM per channel setup. Otherwise, the memory system still ran at full DDR3-1800 CL7-6-6-14 setting: not bad at all!

The configuration passed the other memory and benchmark tests as well, however we don't feel comfortable with running the DDR3 memory in the long run above 1.9 volts, even with extra cooling, due to potential drastic lifespan decrease.

In summary, there is no single DIMM per channel limit here yet: if having a good mobo with a set of top-notch DIMMs like these offerings, and willing to spend some time tuning the stuff, you can still have your 4GB DDR3 cake, and eat it with full bandwidth and low latency. But, it will be hot, take a lot of power and, last but not least, still cost hell of a lot of money. µ