It's not a V bottom, it's not a U bottom, it's a Nike swoosh recovery - Greg McLenon, Hotovec Pomeranz
The information covers Tejas, a future chip expected in 2005, which has a different type of hyperthreading - something Intel croaked at its recent Developer Forum.
Prescott, as we revealed here earlier this year, will have a version using the 775 pin Land Grid Array and a whole new set of pins to confuse motherboard vendors and the rest of us.
According to the article, confirming other details we discovered, Intel has a 1066MHz front side bus in store, and Tejas will start at about 4.5GHz.
It will have eight new instructions. We'll ask Louis Burns, Intel's desktop man, what these are, and if he doesn't tell us we'll make some up for you, sharpish.
Tejas is due to be released in the second half of next year, but as PC Watch points out, the memory type corresponding to this is DDR 2 at 533MHz. Optimists reckon that memory type might be ready next year.
Land Grid Array - already used by IBM - has the advantage that it is a flexible pin design that allows for other developments as they're invented.
PC Watch has some die sizes and cache details for you at its site as well. It also speaks of Grantsdale, which as we've pointed out is a PCI Express ready chipset.
There's much more here, and Babelfish has a great Japanese-English translator these days. µ
2004 Prescott, Tejas chips to have new socket, chipsets
Intel confirms Tejas, Prescott, Canterwood, Springdale details
Intel Developer Forum Spring 2003 coverage
What the 13 Prescott New Instructions really do
10.20GHz Intel Nehalem slated for 2005
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