Rambus show off Terabyte bandwidths
RAMBUS was showing off the first tangible parts of it's Terabyte Bandwidth Initiative. They announced it less than a year ago, and we are at working silicon already... not bad.
A DRAM emulator pushing 16 Gbps
The short recap is to get a single chip with 1TB, that is terabyte, not terabit, of on- and off-chip bandwidth. Optical interconnects can kiss their shiny metal logo. To do do this, you need a single differential pin pair to carry 16Gbps, and put 512b wide interfaces on chips. Each one works at 32x signaling rate with their Flexlink C/A technology providing a little routing leeway.
The test chips above basically do just that, only one channel though. There seems little reason why you couldn't replicate this over and over again, providing some serious bandwidth. With luck, the hard work is done, time to productise it. ยต
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It'd be nice if they could improve storage subsystems to the point where this massive amount of bandwidth could actually be exploited.
there is GDDR5-hardware out there that does more than 7Gb/pin/sec, which compares quite nicely to 16Gb/diff-pair/sec. And those GDDR5-parts you can buy right now, including real memory, not just a nice prototype without real memory.

The essence of the story is that going to differential pairs requires a huge jump (x2) in performance just to compensate the loss of half of your data-pins ...

cheers
Their previous history is one of deceit
low bandwith and modules running way to
hot.
I hope they wither and die.
Once the memory makers got together and decided on a standard for memory modules. Rambus left the meetings and ran to the patent office trying to make the tech proprietary. They lost.