All you are doing is competing with your customers - Eckhard Pfeiffer, to Intel
The cell is a high performance low latency controller interface to an XDR DRAM memory subsystem. The general purpose cell, said Rambus, is independent of the logical memory controller, providing a wide on-chip CMOS level signalling interface to the memory controller logic and a high speed differential Rambus signalling level (DRSL) interface to the XDR memory system. ยต