Intel's Dempsey set to knuckle AMD's Toledo

THE DUAL CORE WARS are heating up, but you won't see it until next summer. The fight was picked by AMD, the capabilities have been in the K8 core since before day one. Intel is in the position of being reactionary, and starting with an 'if they can do it, so can we' project. Make that projects, there are two of note, one reactionary, the other will be the one to watch.

Let's start out with AMD, it is the one which has the best thought out strategy. The use of HT as an interconnect has paid massive dividends for AMD with the K8 core, and that will extend to the dual core products. Every K8 has a HT switch on chip, it is necessary for the CPU to function in a glueless SMP environment.

When AMD designed the K8s, it put an extra port on the onboard HT switch, something that cost it silicon area, design and debug time. It ate that cost for two years, not acknowledging anything up its sleeves. The reason that AMD is so well positioned for dual cores is that it can take another core and slap it on the open port and with little or no debug time, have a solid dual core chip.

All is not well in AMDville though. The dual core chips do lack one thing, a second memory bus, the pinouts on the socket are simply not there. The two chips will share a single 128-bit memory channel. If you look at the PR ratings when going from a socket 754 to a socket 939 Athlon64, you will see that values this at about 1-200 PR points. Expect the dual cores to take a performance hit here.

On the up side, the communication between the chips should be much much faster. This means for things like cache related traffic and other housekeeping details, the overhead should be much lower. How this will factor into multiple dual core chips on a motherboard is probably anyones guess, and most likely will be application and OS dependent.

The take home message is that AMD planned this from the start, and the chips will be better in some ways and worse in others than two cores in two sockets. I would expect them overall to perform about as well as two separate chips a speed grade down.

Intel has a big problem with dual cores, and it all revolves around the bus. AMD does not have a bus per se, everything is point to point links connected by switches. Intel has everything on a single shared bus, all the CPUs and the northbridge. If you have a single CPU, you effectively have a point to point link between the CPU and the northbridge. Dual CPUs brings you a shared bus, two CPUs and a north bridge. Once you get to four CPUs, things get really ugly.

There are two problems here. The first is that the chips have to fight for the bus. If CPU0 and CPU1 want to access memory, one has to wait. AMD gets around this somewhat by having a memory controller on each CPU, and while it helps, it also has a different set of problems. Either way, traffic congestion is a problem on a shared bus.

The other problem is an electrical engineering one. Vastly oversimplifying this, the more loads you put on a bus, the harder it is to design. Until earlier this month, the Pentium 4 bus was at 800MHz for a single CPU, 533MHz for a dual CPU setup, and 400MHz for a four way system. This nicely shows how the problem manifests itself.

Looking at it from another angle, the more CPUs you have, the more contention you have for the bus. Also, the more loads, the lower the maximum bus speed you can get away with is. It is a vicious cycle, and the only way to get around it is to have each chip use the bus less. This is why you see Xeons coming with larger and larger caches, and 4 ways tend to have larger caches than 2 ways.

This solution tends to work well, but it makes the chips have a much larger die area to hold those huge caches. This makes the chips more expensive to manufacture, lowers yields, and increases power consumption a little. Since the chips that need large caches are aimed at the top end of the market, the extra expense can easily be covered by pricing the chips higher.

Both of the problems come into play with making a dual core Xeon. If you put two cores on the chip, you make it bigger. Duh. You also put two loads on the bus which slows it down, and adds traffic. To counter the problem, you add more cache, and since it is dual core, you most likely add twice the 'more' number. This chip gets bigger and bigger and bigger. Not ideal.

Unlike AMD, Intel is stuck with the bus they have until Conroe and Tukwila bring us CSI. For a dual core Pentium 4, the engineering associated with a wholesale bus change is simply not economically feasible. It could be done for the chips, but doing the chips, the motherboards, servers, and all the associated testing and validation is another story. Since the the replacements are already slated for one to two years after the dual core P4s first hit the scene, it would be money rather foolishly spent.

Since we know that there are dual core P4s coming, and presumably they will work, how is Intel going to deal with these problems? Well in two ways, and the codenames are Paxville and Dempsey, with Paxville being the reactionary part. When Intel found out how far along AMD was with dual cores, it came up with Dempsey. It was more of a stumbling around with its proverbial pants around its proverbial ankles, and Chipzilla noticed the ground approaching their nose with frightening rapidity. Dempsey was the dual core product that was 'planned', but would not be out quickly enough to counter AMD.

Paxville is simply two Pentium 4 cores bolted on to a chip. It appears to the bus as two loads, and has all the associated problems with two chips. Slower bus speeds, higher contention, etc etc etc. At best it is a crude weapon to fight back with, and I don't expect a great leap in performance here.

On the up side, due to the fact that it has a shared bus to begin with, there should be no loss of performance over a dual chip setup. A dual chip Paxville system should be about the same in all respects as a four way Xeon system, and a four way Paxville should be about where an 8 way Xeon is.

This is both a blessing and a curse for Intel. I would classify this chip mainly as a counter to the AMD dual cores in name only. It will be a face saver for companies like Dell, so the sales people can say 'we have them too'. Overall, I don't expect great things here, it is more something to keep from falling far behind.

Dempsey is the chip to pay attention to. It will be out after Paxville, and it will be the first true dual core chip from Intel. What Dempsey brings to the table is bus arbitration logic in addition to the second core. Instead of fighting for access to the bus, the cores in Dempsey will talk to the arbitration logic, which will then fight for the bus.

In this way, the chip appears to be a single load on the bus, you can have the best of both worlds in most respects. You can have eight cores with the bus speed of a four way device, and a single chip infrastructure with 2 cores worth of CPU power. It does nothing for the overall amount of bus traffic, but since that bus can be clocked higher, the second core is not purely negative in this respect Overall, not a bad deal, and dual cores done as right as can be on a shared bus.

Now Dempsey is not perfect. More cores need to be fed from memory, and there is no more of that to be found in the Intel design. Add in that Dempsey's arbitration will probably add in a little latency, and you have slightly worse performance than two separate cores, but nothing nearly as bad as the dual core K8 hit.

Dempsey will be the star of the Intel dual core lineup, and I expect it to give the server benchmarks a good kick in the pants. I think the tradeoff of a little latency for higher bus speeds is a good one, and is long overdue.

The whole concept of dual cores is nowhere near as simple as most people try to make it out to be. There are tradeoffs galore, and no simple answer to any question. Looking at the whole market, I would think AMD has the lead on the first generation, but Intel is not one to be counted out. Don't expect much at first, but they will come back strong.

A couple of notes about the upcoming dual core chips that don't really fit in the above article. The desktop dual cores will be rebadged or slightly modified versions of the server chips. The much touted Smithfield name that has been making the rounds of late is nothing more than a Paxville pressed into duty as a workstation and high end gaming chip.

More importantly is a nomenclature change. Intel saw the problem of cores vs chips vs sockets, and how it would confuse both laymen and engineers alike. It came up with the letter S, which is probably not copyrightable either. When talking about dual, quad or octal core chips, Intel uses the letter S for socket to refer to the physical chip. If you want to refer to a Paxville chip, you say it is a 1S chip, not two cores. If you have a four way Dempsey based system, you have a 4S system. This allows you to refer to either the sockets or the chips in a sane way. The sooner people start using this terminology, the sooner my head will stop hurting. µ