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More details about AMD's Griffin tip up

Overview and trivia
Mon May 28 2007, 10:29
AMD'S UPCOMING Griffin "platform" is a strange amalgamation of bits at first glance, but it all makes sense in the end.

As with most new architectures nowadays, the devil is in the details, or at least the good stuff is. If you only look at the "OOo Impress" view, you will miss all of the good bits.

On the surface, Griffin is a ground up reworking of the K8 to be a mobile component. All the enhancements you would expect are there, and it looks a lot like the normal K8. It isn't a question of what AMD did but more how it did it.

Let's look at the parts that didn't change all that much, the cores. There was no circuit-level reworking of the core, it is almost exactly the same as the older K8s. The changes came in with the power management and related infrastructure, the so called uncore.

Each core is run off its own voltage plane, so core 1 can be at the full voltage and frequency while core 0 is at the minimum. They are truly independent, Core 0 can be going full tilt at full frequency and voltage while Core 1 can be at the bare minimums for both. Neither core can be fully shut down however, they will always be minimally awake.

There are three voltage planes, VDD0 and VDD1 for cores 0 and 1 respectively, and VDDNB for the north bridge parts of the core. If you have to pick one thing that separates Griffin from K8 or even Barcelona, this is it.

Other than the power planes, there is one other somewhat major change to the cores. Some of the more advanced microcode, especially in and around virtualisation, was pulled in from Barcelona. There was no circuit level re-working, but some changes were made where applicable and easy.

Griffin has DDR2 and HT3 both of which Barcelona can do. On the surface, it looks like Griffin is the K8 cores with the Barcelon uncore bits. That is not correct. The new uncore parts hit many of the same checkboxes that Barcelona does, but they are independent projects, the bulk of Barcelona was done is Austin while most of Griffin was created in Boxborough.

The reason for this was pointed out by Griffin architect Maurice Steinman - you don't want to pay for performance you don't need in a laptop CPU. There are obvious parts to this philosophy and some very non-obvious tradeoffs.

The obvious are things like dropping memory drive strength at the cost of DIMMs per channel, dynamic scaling of HT width, and autonomous hardware control of DRAM refresh state. These all fall into the category of don't use what you don't need, and don't spend the wattage on doing so.

The more subtle ones start with the clock, or clocks. In the K8, everything ran at core speed. In Griffin there are two PLLs, one for the cores and one for HT. On the most basic level, this allows the memory controller to peak at a much lower speed than on its predecessors, saving a ton of power. It can also wake up independently of the cores, a massive boon for chipsets with integrated graphics. This was a sore spot with older Turions. Griffin runs the memory controller at memory speed not core frequency now.

The clocks themselves are much more flexible. Where the old K8s bottomed out at 800MHz, Griffin will happily play DVDs at 250Mhz. Whether or not this makes it into the final BIOS is anyone's guess, but the capabilities are there.

The cores themselves have two ways to scale, the normal power of two divisors, IE 1/2, 1/4, 1/16th etc, and a divisor that works on top of that. The divisor works by pulse dropping, and that is exactly what it sounds like. If you drop every fourth clock, you end up with 75 per cent of the speed you dialled in. Coupled with the other divider, you end up with more than enough speed choices.

Griffin can throttle itself up and down, and independently do the same for almost all IO mechanisms based on need. It can also do the same based on temperature. The older parts needed a separate thermal monitor, Griffin has them on die now. Additionally, the chip can monitor memory temperature and base memory speeds and usage on that. While this isn't anything new in the grand scheme of things, it is the first time it has been implemented on an AMD CPU.

With all these changes, especially to the IO infrastructure, you would think Griffin would be quite different from its ancestors. Remarkably, that is not the case, it uses the same socket S1 as other AMD mobiles but it is keyed differently. The pinouts are not the same, so it is not physically compatible, but it is electrically compatible. There is no reason you can not take an AMD 780M chipset and use it with any other AMD component, and no reason you can't take any AMD compatible chipset and have it work with Griffin. It may not make sense, and you will probably lose most of the advanced features on both sides, but it will work. All you need is a little wiring work.

In the end you get a CPU that is designed to be mobile. It is not a clean sheet design for the cores, but is for everything else. AMD put the effort in the parts where it pays off, not where it isn't needed. We will see how well it ends up working early next year.

One last little bit of trivia for you about Griffin. The A0 silicon came back to AMD on a Friday, first silicon always does that just to ruin your weekend. By Sunday, it was booting Windows. µ

 

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