Intel's Prescott - the speculation mounts

What do we know so far? There are the following architectural changes which Ace's says chime in harmony from several sources.

Those include SSE-3, which we believe here will be called communications streaming architecture (CSA), 1MB of level two cache, and an improved version of hyperthreading.

But Ace's also has reason to suspect Prescott will also introduce a bigger level one data cache as well as a trace cache that can shove through over three micro ops per clockcycle.

You can find more at Ace's , as well as a set of very useful links to other informed speculation.

We suspect Intel may use its Developer Forum, which kicks off in Rosicrucian city San Jose, to give us some more Prescott stuff to chew over. µ