The report, dated 22nd of June 2004, show some interesting examples of erratanotbugs. For example, R9 is described as "System bus interrupt messages without data which receive a hard failure response may hang the processor".
So far no workaround is available for this bug.
R16 describes a system hanging as a result of a fatal cache error, while R19 describes a parity error in the L1 cache which could cause the processor to hang. There's no workaround for this one yet, in this stepping.
There are bugs in all chips, although the more complex the design, the more bugs can be expected. The document Intel released on the 22nd of June describes both 478 pin and LGA 775 microprocessors. It's what's inside, not the packaging, which is important here.
The channel tells the INQ that there may not be as quite as many Prescott Pentium 4s around before September as we might expect.
So that gives Intel time to fix some of the errata found in the PDF, here, perhaps by attempting different so-called "steppings". µ