PA Semi's multicore chip challenges big boys on power, performance

Today it announces a product line called the PWRficient architecture, and the first chip in the line, the PA6T-1682M, will be out in mid-2006.

See Ex-Alpha designers set to unveil first CPU and Intel in a tangle over Tanglewood chip design.

The big names on the board start with Dan Dobberpuhl, ex-Alpha and SiByte and Jim Keller also of Alpha and AMD where he did some of the K8 designand surrounding infrastructure. A late addition is Pete Bannon, Intel fellow, Alpha alumnus and Itanium person, but we won't hold that against him.

What is this company doing? It is making a new PowerPC chip with a high level of integration. It is also almost totally modular, so you can mix and match components until you get bored. Lest we forget, the current in vogue buzzwords, because it is focusing on low power and performance per watt. Just about every trend coming to mainstream CPUs is implemented here in a more advanced way than others are talking about in their 'coming soon' slides.

The PA6T-1682M is less of a CPU than a system on a chip. It is aimed at the embedded market, where things like size and component cost are paramount, but distinctly secondary to power. The power part is covered, this dual core CPU only takes up 13W typically, and 25W max to get you over 1000 SPECint and over 2000SPECfp per core. Remember, each chip is two cores, so double the SPEC numbers per socket.

The integration part is more interesting. The PA6T-1682M takes two PPC cores, the PA6T and puts them on an extremely fast crossbar called CONEXIUM along with shared 2MB L2 and two DDR1066 controllers. The architecture will support from one to eight CPUs, one to four memory controllers, and one to 8MB of L2. The L2 is actually on the crossbar as a separate entity, not on the cores themselves.

The next part is what you normally consider the computer, but PA Semi put it on the chip. It has crypto, iSCSI, XOR, and TCP/IP accelerators on the die. It also has eight PCIe controllers each capable of one to 16 lanes, four GbE lanes and two 10GbE lanes. All of these can talk through 24 SERDES lanes, PCIe takes 1 per 1x, GbE takes 1, and 10GbE takes 4 lanes. Mix and match however you want.

The accelerators and the IO all talk through an interconnect dubbed ENVOI. ENVOI in turn connects to CONEXIUM through a bridge. This means that all the pieces are at most one intermediary away from their destination, and the relevant ones are grouped much more directly.

That lessens latency a lot, and adds to performance, especially for networking. Think about what AMD did with pulling the memory controller on board, and then apply that to everything.

Since everything is a node on an interconnect, you can add and delete parts almost at will, certainly much easier than on conventional architectures. There is a single core due out after the PA6T-1682M, and a quad core after that. You can add memory controllers, SERDES lanes, and any other part until you get bored. P.A. Semi will bring specific parts to market, but if you are high enough volume, they can custom tailor one for you.

What you end up with is a flexible line of chips that won't cost much to design a solution around. If the performance numbers hold up, we think it will do very well. It took a far-sighted but common sense approach to making a chip, and sweated the details. µ