Glew has posted his up to date CV on a web site, and writes about an architecture he proposed for AMD's "K10" chip - which would include multilevel everything, and would support implicit multithreading, speculative multithreading, skipahead multithreading and lightweight user level forking.
He says in his CV that he isn't disclosing any AMD future plans, but that these are things he had proposed but have been rejected.
The CV mentions that he wrote an instruction set architecture roadmap, a proposal that might be followed up by AMD in a long term plan for instruction set extensions "post AMD 64".
His CV is here. µ
For real this time
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