Lite-On coughs up for microprocessor licence

I know this guy (Charles Moore) the inventor of the Forth computer language, and one of the greatest untold processor designers of last century.

His first processor used parallel long instruction word principle in the early 80's, years before Intel discovered it, and was the highest performing processor for some time (even though it was only based on an gate array). His next processor, also customised to run Forth, also was customised to run C, and the modern version (shboom, the other part of the Moore patent portfolio) was the fastest Java processor for sometime.

Everything was not as good from there on. I spoke to Charles during the Australian Forth Symposium in the late 80's, and he was interested in doing an 20bit processor at that time (yes, not 4-32bits like most interface chips of that period) shocked, I advised against it. Soon he started his own low cost garage custom Minimum Instruction Set processor design, that ran wildly overtime (and presumably the budget was not the same either) and came in under expectation, and it used an new Forth like language that was lesser than his traditional Forth and basic maths and shifting (in order to achieve even an multiply), But he made some revolutionary advances there too. He made an processor with IO, custom programmable graphics instruction set and output, and onboard memory, and in something like 6 thousand transistors, maybe it was something like 12 thousand transistors. He had worked out and way to run the processor at something like ten times what the normal design rules would allow, asynchronous timing (or was that the previous processor) and his own CAD system for custom silicon in around 4K running on an basic PC, based on his new Misc machine language. But things once again did not turn out favourably, bugs held back the design, and the initial speculated speed was not realised years later, though it had very low power consumption. The bugs require some special programming. But it was an learning process, as he figured out how to make custom silicon by ignoring the normal design rules. Objectively, it was an good idea, because the units were so simple in complexity, you could customise the lot and speed up the processing speed, like the unique 10Ghz? IO ports technology, by ignoring the speed restricting design rules (that are there to ensure ease of design for bug prevention in complex circuits). There was an number of chips based on this design, one funded by NASA startup venture (which favoured the super efficient Forth language in times past, even the original Mac had an Forth heritage, but was abandoned too early on, but came up latter in firmware again).

Lastly, he then announced his plan for an super fast 18 bit parallel processor array. The years went by before funding became available, and the processor did not turn out as much as originally thought it would, But super low power (I say all this in relation to process it uses) each with an pool of memory, but instil seems even more restricted in processing ability than the previous Misc chips.

Unfortunately, I went one way and Chuck went another. Chuck went to Minimal Instruction Set computing, and my designs went to an practical efficient minimum to handle complex tasks instead. I learned many things from my time around the very clever (top programmers/designers) in the Forth community, that kept the dream alive for so long in the face of "C" Language competition, by doing it simpler, smaller, faster, more reliable and more efficient (Forth is an high and low level language, sometimes, in the ancient past, compared as next to assembler in efficiency and potential complexity) these are the sort of corner stones I still share with them. It is also the way that the whole industry should have gone. Not that we should do incredibly complex large projects in such incredibly detailed ways, but we make it easier to achieve these cornerstones. My design in an Vista like System, with new hardware security and processing systems, would maybe still fit in 10MB, and be scalable from watches up. All I can recommend to Chuck and his team, is that sure the new chips are suitable for an range or applications, but add, at least, one full fledge master controller with an full addressing range, and more powerful instructions and arithmetic, and chips with an array of these sorts of fully fledged units and some more memory busses, and pool more memory for some of the processors (the new Intel designs, though more complex, are moving towards what I have been hoping for over the years). I have seen the future of parallel processing an number of times, and it is here now, and powerful, even Intel in jumping onto the mass parallel array. Do versions on the most suitable, and the best available design processes (by special arrangements, like if that new Asian 3D transistor architecture in suitable). It won't be anywhere near as complex as what I think we need, but hopefully it should ensure its future.
(Somebody will un-doubtly come across, and tell him about this thread).

My apologies, for any grammar, spelling, and factual areas, it is 5 am and I am not the best.


Wayne.