Yonah emerges from Intel whale. Sossaman watches

INTEL WHEELED in Ronny Korner, CPU validation manager at Intel Israel to talk about Yonah. Yonah dual core will be a 65 nanometre, 90.3mm square, 151 million transistor, with 2MB of shared cache, support for VT and SSE3, and with a 667MHz front side bus.

It will be available in two sockets, PGA 568 and BGA 479, and will launch in Q1 of next year. He said Intel has included a totally new power management unit which negotiates with the chipset. The bus is optimized by power and performance, and the system sees the Yonah as a single entity.

The first choice would have been to join two Dothans together but that wouldn't deliver the power performance Intel wanted. Full optimization means lower power, smart thermal and power management, and elimination of redundant logic, he said.

He said that improving media performance is a complex architecture task. Intel profiled a lot of apps running on Dothan and what it learned from these, it improved the architecture to optimize them. Better decoder bandwidth meant the Micro OP Fusion was extended to SSE2 LD-OP instructions, and the 128 bit SSE2 instructions are now handled by all three decoders which Korner claimed gives up to three times decoder bandwidth.

Sorry for the picture of the Yonah die below.

Both cores can use the full size shared L2 cache, with shared data accessed from the cache minimizing the bus traffic. The chips include dynamic cache allocation.

He claimed that Intel will be able to extend the battery life of Yonah over its Dothan and Banias cores by looking at several features including Vcc cache design, and by improving the power process technology. Cache is a big element in average power, and turning it off while retaining data integrity and memory coherency is important. The chip will use dynamic smart cache sizing, enhanced deeper sleep and the low Vcc cache design. Battery life will be comparable to that of Dothan and Banias, said Korner.

A hardware based algorithm considers the percentage of time the CPU is in active state, hard coded. Yonah adapts its effective cache size by syncing it with the system memory, and cache ways are turned off physically as well as logically, which reduces power.

In deeper sleep, the Vcc is at the cache sustain level, and is invoked when the cache is empty and the cache ways are powered off, with the voltage reduced to the core retention level, reducing leakage for the entire CPU.

Each of the cores has its own sleep state, controlled by the operating system using a new MWAIT (Cx) instruction. The hardware interacts with the chipset. Sossaman is a derivative of Yonah targeted at high performance low power blade and rack servers. The chip can support up to 64GB of memory.