The 65 nano chips use a second gen version of Intel's strained silicon, copper interconnect, and low-k dielectrics.
The SRAM have a .57µ2 cell size, and are 4 Mbit chips. Each cell only has six transistors - Intel's analogy is that 10 million such chips would fit inside the tip of a Biro.
According to Sunlin Chou, general manager of Intel's technology group, the 65 nano process extends the life of Moore's Law.
The chips will use transistors with gate lengths of 35 nanometers. The process will integrate eight copper interconnect while the low-k dielectric will cut down on power consumption and increase signal speeds inside the chips.
The proof of concept chips are being made at Intel's 12-inch D1D development fab in Hillsboro, in the state of Oregon.
The firm said masks for the chips extend the existing 193 nanometer wavelength lithography equipment. It won't have to replace the current 90 nano kit, but can modify it, it claims. µ
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