Intel talks up Floating Body Cells

INTEL IS GOING to put out a paper tomorrow at IEDM about something called Floating Body Cell memory, a kind of embedded memory with a lot of potential benefits. The full paper will be put out Tuesday, but if you are interested in the basics, read on.

There are two types of embedded memory in common use, SRAM and Embedded DRAM (eDRAM). SRAM has 6 transistors per cell making it big, but it is fast and easy to manufacture. eDRAM has a transistor and capacitor making it more dense than SRAM but also a lot slower and harder to make.

Floating Body Cell (FBC) is in the middle, it has only one transistor so it is dense but also slower than SRAM yet easier to make than eDRAM. Six of one, half a dozen of the other, but it looks to be splitting the middle fairly well. It is still a little early in development, so some or all of these promises may not work out as well as Intel hopes.

The way it works is to use something called the history effect. When you put a charge in through a transistor on an SOI wafer, it retains some of the charge like a capacitor. You can tune the retention based on the thickness of the Bottom Oxide (BOX) or the voltage differential.

There are two organizations that have done a lot of work on FBC, Berkeley and Toshiba. Berkeley started it out and Toshiba seems to have pushed it to modern processes. As you can see above, there are two differences between the Berkeley cell and the Toshiba one, the BOX thickness and the Substrate voltage.

The brighter among you might make the correlation that the thicker the BOX, the higher the voltage you need to have the 'history effect' keep a charge in the FBC. That is the key to all of this, and the main problem.

The key is you tweak the BOX to tune the cell, you can make the history longer or shorter, operate a higher or lower voltages, and probably a bunch of other characteristics. That is the good, the bad is that the FBC is embedded in a bunch of logic.

When you start mucking about with things like the BOX thickness and the chip voltage, you also affect the logic transistors. They might not be as amenable to the tuning you are doing, in fact it may make them run considerably worse than they did before the tuning. The two processes may have diametrically opposed goals.

The breakthrough from Intel is decoupling the tunable parts of the FBC from that of the logic surrounding it. They put a Front Gate (FG) and Back Gate (BG) on either side of the FBC instead of above and below it.

You can tune the BOX and the voltages for the logic transistors that make up the bulk of the work you are doing, and then tune the FB and BG through other means. What means? Simply draw them bigger or smaller with traditional methods.

Then you can tune the BOX and voltage for logic and draw the FG and BG in accordance with the parameters set for the logic. It is basically a win/win for the FBC, the knobs that affect the logic are fixed by the logic and the tuning for the FBC does not affect the other parts of the chip.

How do they make it? They start with a 3D transistor similar to the tri-gate parts you hear so much about. The particular ones they are going to talk about are done on a 65nm process, and as you can see, they basically lop the top off the gate to make the FG and BG.

The open questions are the usual ones. Can they make it on a mass production scale? Will it work in the real world? Will Benji get help for little Timmy before he falls off the cliff? Will it work on bulk instead of SOI? Who knows, but time and a lot of research will certainly tell. µ