AMD seeks to outflank Intel on virtualisation

YOUR CORRESPONDENT was shocked to read on an AMD virtualisation web page that most servers operate at less than 15 per cent capacity, which is a terrible waste of computing power and energy.

At that usage figure what general purpose server is ever going to need the low latency advantages of HyperTransport or enhanced PCI-E? In that low utilisation world the PCI bus still has a future. Virtualisation is going to have to deliver greater efficiency gains.

In the virtualisation era, data centres would be specified on a resource level - the number of cores, the amount of RAM and storage, etc. If a data centre would gain from Torrenza's quantum factor, it would be possible to do the same amount of work with a lot less hardware.

When co-processor accelerators are embedded into the CPU and chipset and an accelerator card is plugged into the HTX slot as well - effectively a tri-level co-processing system, virtualisation could allow these accelerators to work together or be assigned individual workloads.

When virtualisation becomes dynamic - that's to say, hardware allocation would automatically vary with load - system latency or response time may prove a critical measure.

To put latency into a monetary perspective, the CTO of the New York Stock Exchange said at this year's AMD technology analyst day that one of his company's more sophisticated customers had said that one millisecond reduction in latency is worth 100 million dollars a year to the bottom line.

If an application consumed all the local CPU and memory resource, and additional capacity was added, which happened to be external to where the core application was running; if system latency is poor, the program may incur undesirable delays.

In a HyperTransport Consortium HTX verses PCI-E FAQ, the consortium used a HOV lane (high occupancy vehicle) traffic analogy to explain the best use of the interconnect's super-low latency:

“When traffic demand is high - i.e. in compute-intensive applications - it is the fastest way to destination - i.e. lowest latency to compute results. In some cases, the only way to reach it in due time”

“When traffic is low - i.e. in normal compute applications - its time-saving potential is minimal when compared to any fast lane - i.e. a PCI Express interface could prove adequate for the intended purpose” For those not in the US, a HOV lane can generally only be used by vehicles with a minimum of two persons. So come rush hour, those who can't use the HOV lane arrive home later than those that did.

For a virtualisation platform to truly shine, four critical components will need to be in place:

1.A general purpose CPU that excels at mainstream applications.
2.An on-chip memory controller that allows the platform to scale its memory bandwidth as additional CPU modules are added.
3.A high bandwidth low latency bus that enables peripheral communication and exchange of data unhindered.
4.An accelerating enabling platform that demonstrates a quantum leap in performance.

AMD already has the last three of that list in place. But what the company is missing is a general purpose CPU that is at least the equal of the Core device. At this year's AMD technology analyst day, corporate VP Randy Allen claimed that Barcelona changes the game in four different areas: Investment protection, power efficiency, virtualisation, and most important of all - performance. If Barcelona does change the game then AMD would be holding all the virtualisation aces, which would give the company a solid foundation from which it could attack the virtualisation market.

If virtualisation was mainstream today, AMD's market position wouldn't be as weak because those three items that the company has in hand would compensate for its underperforming CPU. Intel can only tout a great microprocessor - the chip giant still has to deliver those other three items on that list.

Inferior latency may prove Geneseo's Achilles' heel
It was said at the IDF Geneseo keynote that improving PCI-E latency was a laundry list item that had to be addressed. Bear in mind also that Geneseo has to maintain backwards compatibility as well, so it's not a clean sheet approach. Impaired latency performance could result as undesirable baggage may have to be carried over.

As a counterpoint to that, Intel did say in its Geneseo white paper: “In addition, it is expected that most Geneseo features will be optional- meaning that designers only need to incorporate those features that provide performance gains for their specific systems.” Is that another way to say that those legacy undesirables can be left out?

Now that might be perfect for standalone servers. But in a heterogeneous virtual world could resources in the system drag down overall performance if that hardware was set up with those legacy carry overs in place? Also, could additional performance penalties result during dynamic virtualization events when, for example, a Geneseo based resource (server) was brought online for additional capacity, which required that legacy baggage in place? So in today's low-utilisation server world the PCI-E interface is perfect. But in tomorrow's high-utilisation virtual world would the enhanced Geneseo version cut it?

Torrenza has arrived, will Geneseo make it?
Something that should concern the chip giant is the head start that Torrenza has. Intel has said that the Geneseo definition stage is targeted for an early 2008 completion. The company has also said that Geneseo ready products should be available from late 2009, which would give AMD and its Torrenza partners about two and a half additional years to further strengthen their position.

So, Geneseo is still in its gestation period, which means Torrenza has already passed the critical infant mortality period. Also, AMD has its core platform technologies in place, which should allow Torrenza to flourish. Intel still has to bring its counterparts to market - CSI, on-chip memory controller, and Geneseo itself.

If Torrenza fully delivers on its promise, Intel will feel like it just got back into the game only for AMD to then move the goal posts - you can't counter something that is fundamentally superior. It's like the chip giant just launched the best Formula 1 racing engine ever but didn't have time to fully develop the chassis - the F1 car is great for straight, quarter mile runs but any bends will highlight serious chassis limitations.

Considering how important Torrenza is to AMD, the ATI acquisition was a logical decision that makes the company less dependent on third party delivery. That purchase should also ensure that Torrenza eventually becomes a pervasive PC technology as well. Third party players will also play a vital role in bringing Torrenza into the enterprise space.

From what's been seen of Torrenza already, I believe that this technology will prove to be market changing. Also, if Geneseo isn't flawed at birth the chip giant's counterpart will prove critical to its future success.

If Torrenza should make Geneseo look pedestrian, that would be a more serious situation for Intel then when Opteron and the AMD64 platform was launched, as AMD is now an established enterprise space player.

If Geneseo falls flat on its face and the x86 landscape gets turned upside down to AMD's advantage, that failure could force the chip giant's top brass to walk, as they would have presided over two major strategic failings - the other being Itanium.

Whatever the future brings, these next few years for me will be the most interesting to date, as I believe a lot is going to change in many different areas.

Despite AMD's current woes, the company does have its coprocessor, accelerator enabling, and core platform technologies in place. The same can't be said of Intel. But when Geneseo and its supporting technologies are market ready, the chip giant may shock us with another surprise package - just as it did with Core.

In his June 2006 analyst day presentation, AMD CTO Phil Hester showed a slide that said the following: “Successful next generation designs continue to broaden their system-level focus.”

AMD64 has been and will continue true to that statement. Torrenza is clear evidence of that system level focus. µ

See Also
How AMD will seek to limit Intel's Core chip success Part two
AMD Torrenza will be key to keeping Intel at bay Part One