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Intel panics and announces Merom

Silence of the LANs
Fri May 06 2005, 11:15
INTEL HAS FINALLY let the cat out of the bag and announced the Merom clan. I say finally because it is pretty much an open secret that they are coming. Intel was forced into this by a lack of current product and a rash of bad PR. The PR was mostly self inflicted, and I actually prefer the honesty that came forth this week to the usual answering of tangential questions.

I don't know what exactly it "announced", or if it was any more than a code name, but they are 'outed' now, so now the speculation about what they are begins the beguine. Luckily, if you are reading this, it also ends. There are three chips. Merom, the mobile part, Conroe, the desktop, and Woodcrest, the Xeon. They will be followed by Whitefield, essentially a four core follow on to Woodcrest. All of them, except Whitefield, will be dual core from the start.

All of these parts will be completely new from the ground up. The talk of them being Pentium M based is complete bull because these are next generation "brains of the computer". They have all of the features of the current chips, all the *Ts (Socket Ts), and a few more, and of course are 64 bit. The most surprising bit is that they will not have on die memory controllers on Merom and Conroe. Woodcrest will be FBD (fully buffered DIMM) enabled, so look for the potential to have stupidly large amounts of RAM on it.

The chips themselves throw out the failed P4 "Netbust" architecture and are based on the Pentium M philosophy of shorter and more efficient pipelines. I have heard 12 or 13 stages from several people. Don't look for clock speeds anywhere near that of Netburst products, more in the 2.5GHz range for the desktop parts. That is not to say that they won't be fast, as Intel so thoughtfully said two American IDFs (Intel Developer Forums) ago, they will be four "issue" wide, and undoubtedly have a better "front end" and cache setup than any of the current chips. Look for a large IPC (instructions per cycle) advantage over the current PM cores, and a truly huge one over P4 parts.

All will be FSB (front side bus) based until Whitefield brings CSI (common system interface: ring enabled HT) to the party. The FSB will clock faster than the current chips, but even Intel hasn't figured out by how much yet. Here is some predicitive speculation. This is the weakest link of the chips, but if you look at the Twin Castle and Blackford results, Intel has more than the engineering talent to minimise any deficiencies over HT or CSI. DIB (dual independent bus) effectively provides the same topology for a two socket system as a P2P layout. They will do all right here.

Merom and the rest are why Pat Glesinger can grin when he goes to bed at night. It's not just the fact his wife makes him a nice cup of cocoa. He and the rest of the Chipzillites will bring Intel right back to competitiveness on the core front. When the followup cores with CSI come in, AMD will have a lot of sweating to do. They had better have something damn good in the pipe, because if they do not, Intel will steam roller them.

If you are wondering about the rather anaemic 65 nanometre Pentium 4 based dual core offerings, wonder no more. This is all because all the engineers were pulled off the projects to make Merom a smashing success. The PRs were gagged. The early word is all thumbs up and ahead of schedule. The 65 nanometre process, it appears, is well beyond healthy, and has some surprises lurking.

The chips will be "out" starting in late 2006 with Merom, followed by Conroe, then Woodcrest. We expect them to be publicly shown at the next Spring IDF, and perhaps Chipzilla will lift the veil and show off a couple of early early samples at Fall IDF, if there is one. Nut Intel may not have functional silicon by then.

Intel is back on the scene late next year, barring "execution problems". If you see an Intel exec smiling, it is because she or he knows what is coming and has stopped looking at her or his girlie Rolex. µ

 

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