Computational litho will change the semicon industry

WITH THE CONSTANT decrease of a gap between transistors and talking at the nanometre scale instead of microns, more and more challenges are arising for engineers in the semiconductor industry.

Today's transistor consists of a mere couple of atoms, and the gap between the holes where transistors are located is constantly shrinking. Too many things are taken for granted.

Short explanation how transisotrs are actually made

If you reduce the gap too much without adjusting the current, the power spark will not come to the transistor and 0 will remain 0, not changing itself into one - leakage. As the gap will continue to decrease into 45 nanometre and 32 nanometre sizes, a third party is coming into the frame and it is She Who Must be Obeyed. Mother Nature.

The problem lies not just within the gap itself, but in the way transistors look today - they have lost their perfect shape and the light is now leaving a different image on the wafer than it should.

Sadly, lens has much more work to do than in the first picture, and actual look of the cells is the problem enhanced by ever-decreasing gap between them

Missus Nature comes with a certain set of constraints we call physics. One of the biggest problems that the semi industry faces is how to channel the light to the photosensitive area of a purified silicon wafer.

While many players of the industry are talking about immersion, or putting the wafer in water and then continuing the manufacturing process, several engineers in Intel are working on something else, called Computational Lithography.

Ingenious move by Intel Research team - forget analogue, let's print pixels!

In fact, this is nothing else but digitising the lithography process - instead of using classical analogue methods of manufacturing wafers, computational lithography calls for pixel masks. Just as digital photography replaced classical film based one, computational litho should change the way chips are being made, and this is especially true for advanced 45nm and 32nm manufacturing processes that are coming just around the corner.

In a way, these Intel people invented a computational model how wafers should be lit to get the transistors looking as planned and more importantly, in working condition. Now, why did no-one come up with this earlier? Was Mother Nature dozing, or something? µ