The wonder that was to have been the Alpha

THERE'S A VERY INTERESTING thread on the Usenet comp.arch group which discusses what the engineers at Compaq had in mind for the Alpha chip before its progress was so rudely interrupted by events.

According to the thread, Alpha's future included vector computing, with a new architectural state, with the processors aimed at the high end of the scientific market.

In one poster's words: "...to carve out a niche for themselves while tITANIC ruminates in the low & mid range of the commercial server 'space'."

Compaq architectures were considering a dual core EV8, but considered that symmetric multithreading over four threads was not practical, or rather worth doing.

The "Tarantula" project would "add 32 new vector registers (v31 being 0.0x128) each of which were to hold 128 doubles. It was to be integrated with the EV8 core along with four times EV8's L2 cache for a total of 16MB. "

And L2 bandwidth was going to be an incredible half a Terabyte, with the spidery beast having 32 Rambus memory controllers and 64GB of memory bandwidth.

The clock speed would only have been 2.5GHz and this project was envisaged for 2006, but then as AMD and Intel have only just realised, size isn't everything.

The thread - which has grown many, many legs already, can be found here. µ