Intel's Stoutland to have integrated memory controller

SOURCES CLOSE to Intel Australia provide information about an Intel multiprocessing idea dubbed Stoutland which is slated to have a CPU integrated memory controller and some other unusual features too.

The plans, which are not PORs (plans of record) yet, include 4S glueless sockets using third party XNC and a fully connected CSI. This will provide 6.4GT/s or 4.8GT/s, an astonishing 72 second generation Boxboro PCIe lanes and four first gen PCIe lanes on an unused ESI port as well as six first generation ICH9 lanes. Legacy support will be added through ICH9.

The CPU integrated memory controller will include 4+1 FB-DIMM I and FB-DIMM2 channels, with the latter clocking 800/1066 and providing 32-64 DIMM support per system.

The Beckton CPUs rovide four CSI per socket.

Intel is projecting this interesting technology in the second half of 2009, so it's some way out yet, along with the Thurley "platform", which also has an integrated memory controller and uses the Gainestown four core, eight threads CPU.

The Thurley "platform" is aimed at release in the second half of 2008. More on this anon. µ