The clue was in the phrase "... on a two-dimensional die ...".

@ChemC - thanks. I guess there is more to it than component density. Or maybe the Samsung marketing guy can't to maths either.

It is not 50%. As mentioned by richard, it is a 2d chip, idealized as a square. At 30nm, each 'side' is 30nm, for 900nm^2 per transistor. At 20nm, each 'side' is 20nm, for 400nm^2 transistors. And 900/400 = 2.25 = 225% (of the original, so, 125% improvement).

ChemC

Ok lets do a maths 101.

(new value / old value) x 100

(30 / 20) x 100 = 150

The difference being 150 - 100 = 50% difference.

How is it 9/4?

It is actually 9/6, 12/8, 15/10, 18/12 etc etc.

THAT is how it is 50%.

Although vague, I assume that the article means that the yields are much lower on the 20nm process, but still yields 50% usable dies/wafer.
You are correct that ideally 20nm would be 9/4, 125% more dies/wafer than 30nm.
So, at 100% efficiency at 30nm and 100 dies/wafer, 150 dies would need to be harvested from the 225 dies in a 20nm wafer, 150/225 = 67%.
So, more wasted dies, but more dies/wafer, a net gain for our fair city!

ChemC

Samsung is trying to misleading people, 20 nm class could be anywhere between 20 to 30 nm as they are behind IMFT (Intel/Micron duo) in developing under-30nm NAND.

Any bright spark tell me why 20nm is only 50% more productive than 30nm on a two-dimensional die. Surely, it is 9/4 times (125%) better?