Natural speed and power varients within the same process have existed in the IC industry since the dawn of the IC.

Unsurprisingly, both Intel & AMD have been marketing speed and power varients off the same product family for a long time.

You can make the power #'s seem low when you do the whole ACP and rely on some idle time in the average. While ACP is a nice idea... this is a 65Watt TDP chip. When you consider the relationship between clockspeed and power consumption, I'm seeing a lot of clock this thing down to help power and very little improvement in the chip as you imply.

And stop the AMD marketing spin...

"it's putting out new products, not die shrinks" ... huh? AMD is on 45nm, they don't have 32nm until end 2010 (for SOI - forget the weak attempt to confuse the press with talk of 32nm Bare Si processes), maybe early 2011... how exactly are they supposed to do a shrink with nothing to shrink to? You make is sound as if they have a choice in the matter.

@dave: you forgot to mention the additional 120MByte of L1,2,3 *and* 4 cache to make up for the lack of logic.

Latency is soooo overrated.

Intel should release a 1ghz single core version of the quad core and call it the PIII.