I fully expect as we try to stack more and more layers well see columns of insulated metal or other heat-conducting material put down through holes in the actual silicon to pull heat away and deliver it to the heatsink. It may even be beneficial to have channels of material directing heat off to the side, then up. This will become another logistical puzzle in wiring around the columns while at a minimum cost to speed.

The first thing that comes to mind when reading this article is heat. You're sandwiching everything together and the top layer (in a 2-layer design) effectively becomes the heat conducting medium for the bottom layer to the heatsink. Not good, and that's only with 2 layers. What if we have, say, 5 layers?

The other thing is M-Space. Is this what AMD is planning? The feature of 3D chip design is that you shorten circuit paths. Take for example the Athlon design. The Load/Store units and the Bus Interface units are located on opposite sides of the chip. I would expect these two parts to talk a lot with each other. In a 2D chip design signals have to travel all the way across the chip to reach the other unit. In a 3D chip design you can place the L/S units directly above or below the bus unit, thereby shortening trace lengths and reducing heat. This way, I would expect a 3D version of the Athlon (or any other chip) to become thicker but occupy less die space. I think the most important thing here is the material used.

The problem with 3d chip design has always been heat dissipation.
In 2d chips you can cover either side with a heat sink or any form of heat conduction and that works well.
With a 3d chip, you basically get a N-1 layers of chip which are not cooled.
Solve this, and you get a MASSIVE parallel chip.
Go IBM!

PS: I work for IBM :)