" Some of these commenters should go away and never come back, they are disrespectful.
posted by : UnReaL "

Now there's a Corleone talking. :) We like.

No really: Charlie has done his homework more then a lot of us; Torrenza dictates a HT link between components, be it on-die or in a separate slot or connection. All components ( cores/gpus) are to be landed on HT links. So the convergence should be on the table, spelled and rolled out Real Soon Now (tm) I see the sideport and the memory Hub both as temporary solutions; convergence also saves money.

I’ve been working hardware and software since the days when tubes reigned supreme. The GPU’s will be integrated into the CPU as additional cores. This is the best solution at the lowest price. You will have to upgrade the entire chip to upgrade either component.

What rubbish....
You have Hypertransport or you don't.
I wish AMD would force the HTX bus, it will simply put raw speed on the table for AMD CPU's and GPU's.
Simply make a DIRECT connect!

ati has already commented that it is unlikely they will ever enable the sideport. More ati features for the future that they have no intention of enabling.

No wonder there are alot of people moaning, whining and bitching about the article, its all true, yet even I still use Vista for no particular reason.

Long live Charlie.

Some of these commenters should go away and never come back, they are disrespectful.

Nice article, but the RV770 doesn't use the Ring Bus Memory Controller anymore, it uses a Hub based one which is more power efficient and is easier to use completely the available bandwidth while the RV670 and R600 was able to use only the 85% available bandwidth.

The article states ATI used a ring bus memory controller for the RV770. I thought that was ditched in favor of something different? Please confirm this.

But the thing is, the GPU don't need to talk to eachother much, if one does half the screen and the other the other half it only needs to sync a few items, same for GPU applications, the calculations can be done and the results will be much smaller than the dataset and that and some sync signals need to be exchanged.
In fact the whole reason X2 cards have twice the RAM is that they just work on their own copies of everything and only the output is combined AFAIK, and yeah that's costly but means no need for super-speedy communications surely.

There is no ring bus for the RV7x0 series. They've returned to a PTP crossbar ROP/TF/TU/MC arrangement, with an extra two ALU blocks to fill out the die space.

how about they make it genuinely reliable?

There is no ring bus in RV770 - AMD got rid of it in favour of a 'hub' memory controller in order to save die space and optimise perf/mm^2

Where do you morons come up with this stuff. Its why most of the "internet" review sites and chat rooms are filled with balderdash....


i'm under the understanding that the sideport currently isnt used. that would be a first step.

torrenza. right in the middle of your article that little voice in my head started to whisper ever so silently "torrenza". 
although both chipzilla and daamit are supposed to integrate pci-e onto the die just like the memory controller, i personally would prefer daamit to use it's HT3 tech to link everything together.
this finally could be the "killer app" for HT3 and torrenza. think about it: a multi cpu/gpu combo with HT interconnects and some form of shared memory space. would give daamit at least some leverage against larrabee (if that holds what's promised).
could be some serious numbercrunching machine.

A very interesting idea using HT for interconnect. 

I'm pretty sure that the RV770 no long uses an internal ring-bus.