This is all blah the 0.5 TFlops is all theoretical and will never be reached in a real world application. For example branching performance is still horrible even on the most sophisticated GPUs out there nowadays.
With AMD going to GPCPU architectures and dual video cards already having 4GB of RAM, it makes one wonder why they aren't slapping 8GB of RAM on the Hypertransport bus and sharing it with the CPU?

Wouldn't putting CPU, GPU, and Memory all on Hypertransport finally unlock the technological advantage of the on-board memory controller in Barcelona allowing a huge performance boost overall?

Well, it SOUNDS like a good theory...
Th15 1s tH3 PwN4g3!!!!!!
This is all blah the 0.5 TFlops is all theoretical and will never be reached in a real world application. For example branching performance is still horrible even on the most sophisticated GPUs out there nowadays.
With AMD going to GPCPU architectures and dual video cards already having 4GB of RAM, it makes one wonder why they aren't slapping 8GB of RAM on the Hypertransport bus and sharing it with the CPU?

Wouldn't putting CPU, GPU, and Memory all on Hypertransport finally unlock the technological advantage of the on-board memory controller in Barcelona allowing a huge performance boost overall?

Well, it SOUNDS like a good theory...