Never underestimate Chipzilla's ability to execute - Gilbert Ann Sullivan
I'm pretty sure all chips since the core have been essentially based off the P3.
 
 The additional instruction sets are obviously welcome.
Why don't they simply make a P3 using the 65 or 45nm process? Maybe add some more L2 cache? How much power would that use?
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I'm pretty sure all chips since the core have been essentially based off the P3.

The additional instruction sets are obviously welcome.
Why don't they simply make a P3 using the 65 or 45nm process? Maybe add some more L2 cache? How much power would that use?