Dear Charlie

I see that you have corrected the article, it originally talked about two process shrinks. I still find it unaccurate. As you know Intel doubles everything (but the cache) on Tuwkila but adds IMC and CSI, so it doubles transistor count. and at the same clockspeed it manages to keep Tukwila in the same TDP of Montecito despite using more power hungry transistors (it changes the ratio of logic, comunication... versus cache). 

Thay also increase performance clearly when going to higher clockspeeds (25% more) but suffering the logical penalty on TDP (only 25%, less than I would have expected).

So maybe the article should say "Intel is promoting > 2x Montvale performance, not exactly a high bar to shoot for when you have 2x the cores, QUITE LESS THAN 2x the cache and THE SAME clock. " instead of "Intel is promoting > 2x Montvale performance, not exactly a high bar to shoot for when you have 2x the cores, >2x the cache and a slightly higher clock. "

It is also surprising that you fail to notice taht the amount of L3 cache goes from 24 MB to 30 MB (double would be approximately 48 MB)

Best regards