No, bad taste would be to say "Floating in the Mississippi"

Bodies in the Hudson are like seagulls at the dump, plentiful and an unfortunate fact of life.

Pascal Monett: CPUs have been 3D devices with many layers for quite some years.

Intel in its Best, X48 is NOT Best Choice. Whiles Take 'Er Down to .89?75 volt core, Intel forces 1.24 Minimum thru Intels Main circuits. intel knows there are times outside that range & keeBam, No More Main. Too narrow of choice while all others offer greater latitude in specs. Intel just wearsed out.
So with Hi-K, its much more likely to use entire 1.34 or so voltage without dipping to super low states or BSOD. While another mfg might get Intel CPU to Low,Low State & last longer run better, etc, while Intel makes compromised situation & Enforces it with need for higher voltage to activate Gate with higher resistances than other cpu/mains use.
Drashek

Z-Ram, they have been working on FBC in SOI for years now, but haven't gotten the speed up to equal the CPU.

So isn't FBC like Z-ram then? Surely they'd have to work around existing patents? AMD better get it's butt into gear too since they've been sitting on this for a while now.

Layer of this over newfangled pixie dust under layer of that. Does this mean 3D engraving ?
Are we going to get 3D CPUs in a few years, or is this all just a new version of technical mumbo-jumbo until something really new is found ?

Good info... but had to wince on some of the 'creative' interpertations of it:

" the slideware, however, does say that FBC is suitable for “15nm node and beyond” (about 3-4 years in our calendar"

OK..current =45 nm (Intel at least), 32nm +2 years (~end 09), 22nm +2 years (~end 11), 15nm + 2 years (~end 13)... so at least 5 years out. I think you forgot a technology node. "beyond 15nm" would put it 7 years out.

"It’s all about SOI, and although Intel didn’t like IBM/AMD’s SOI back in the daze they like it enough now that they need it. The FBC (your bit of storage) hangs under the gate and over the 10nm thin buried oxide (BOX) layer, meaning its small, simple (ie: cost effective) and – from what we garner, won’t suffer from the electric shortcomings of current DRAM designs. "

Ouch... first the SOI's we are talking about are different (IBM/AMD use a fairly thick SOI which is NOT the same as the SOI Intel is discussing here) and your 'garnering' on DRAM limitations along with $5 may be worth a cup of coffee at Starbucks.

Intel's issue with SOI was that for transistors (logic), the benefit of SOI did not scale as things shrunk...there was benefit on 130nm/90nm but as you shrank the devices the benefit lessened - ask IBM/AMD how SOI is scaling on the transistor front (and whether the benefits are as substantial as what they saw on 90nm/130nm)

The DRAM limitation is all about aspect ratio (not SOI, or electric-ness). In order to pack them closely you have very high aspect ratios (tall thin devices) in order to get the area needed for the capacitor. The shortcomings are not "electric" it is the difficulty in manufacturing such high aspect ratio devices.

Now I expect I will get flamed for the technical-ness and dryness of this response, but perhaps one reader will leave less mis-informed.

"Floating Body Cells have nothing to do with corpses bobbing up and down in the Hudson River."

Possibly not the best analogy.