that I believe "joe" to be a smart person, although I did not really understand anything he said.

Also I would like some of the high quality ganja that "High_IQ" is obviously powered by.

Should higher Joe. It would be so refreshing to see accurate news on this site. Just get him to dumb it down a bit for the extremely average IQ of most Inq readers.

I always thought 2H/08 was PR code speak for December - if everything goes well and we are lucky.

Stick to the facts, or do not comment!

AT adds: To whom are you speaking?

So what I gather from the article and comments is that we should expect more delays and errata from AMDs 45nm process?

" is it also not slightly misleading to perseverate over AMD not using metal gates? AFAIK, hf/m-g is mainly a way to manage leakage, which is more of a problem for bulk si like Intel uses, less for SOI like AMD does."

OK folks... if you are happy with misinformation, fine... and if you rather attack grammar, since you are seeming unable to attack the actual content, that is fine too.

'AFAIK' - SOI addresses junction leakage, high K affects GATE leakage, these are 2 entirely different sources of leakage in a chip. The same gate leakage problem exists on bulk SOI and bare Si based processes. But don't take my word for it go look at the public IEDM reports and look at the conventional gate oxide thicknesses and Ioff published by Intel and IBM. 

And by the way metal gates doesn't affect leakage related it is the GATE OXIDE (which is the insulator between the gate and the channel). The metal gate and high K are implemented together for other reasons. The metal gate is on top of the high K oxide (which is what is addressing the leakage issues).

But what's the use... if people seem to prefer to wallow in misinformation, then I won't comment further. My apologies for trying to present some information.

is it also not slightly misleading to perseverate over AMD not using metal gates? AFAIK, hf/m-g is mainly a way to manage leakage, which is more of a problem for bulk si like Intel uses, less for SOI like AMD does.

Here, next High K will be 32 NM, it makes shrink more stable & allows slight burst when then going low K, However, due to wires being same SLOW Speed, it is mere ~13%, although tranistors are entire show.

Jo-Jo if there is Oxide in Cyanide metal based transistor its cyanide Oxylate, made in center of SUN, Really BURNS Me UP.DUMBIE. 
Oh, & lets me finish my song:Tel.E.Vision TELL MIST.ER Lee,When he Hears YOU: Hell know Code is Broken-=DOG IS TURNING RED=- hahaha ah 
Being tight race for 4 true cores integrated means MEDIA will Flower Wonderfully & its still YOUR Choice of partner.Also Ultie had to cut 200 entry level igp to 100SE/150, as its first time at starting Gate, get it, gate?hehehe
Soon these advanced Multi Core(4+) (from Slow,Crappy & Crashie(like disfunctional Hippie Pad) 135/90NmXP((double barf until sp2)) nightmare), 4+ cores WILL Rule Complex Home Entertainment Hardware/Software Industry...television.

hahahaha. What way to be Bourne.
drashek

"far more complicated than _what_ you indicate"

Charlie may not fully comprehend the nuances of wafer deposition technologies but his grammar is much more better-er than Joe’s! 8)

- the great unwashed

Gate first simply refers to the integration flow. . Gate first is a process where the high K and metal gate (most likely a thin metal followed by a Poly Si cap) is put in where the conventional materials are done. In contrast, Intel uses a replacement gate process where a conventional gate/gate oxide (Poly Si and SiO2) is 'replaced' (i.e etched out) and the high K/metal gate is put in it's place 

"What this means is they are doing the gate, the critical piece, but not all the other bits like Intel."

This is an interesting (polite way of saying WRONG) interpretation of what gate first means - gate first is simply an alternate approach as described above and has nothing to do with a partial implementation or only putting some 'bits' in. - because of compatibility issues between the high K and conventional gate (Poly Si) materials you can't do it in 'bits' as you imply.

If you don't understand the technology, you shouldn't be commenting on it. 

Oh and by the way, the critical piece is the GATE OXIDE, not the GATE which is the 'bit' above the gate oxide. Due to some technical issues with the GATE OXIDE (what people commonly call high K) compatibility with a conventional GATE (Poly Si) the high K and metal gate need to be implemented together, and not as bits...

"They use ultra-low-K wiring for a claimed 15% reduction in delay, so things should be a bit higher clocked out of the gate."

This is not true either - the improvements in delay come from the transistor (from what AMD described this would be mostly through strain enhancements), the ULK is to avoid the backend wiring from becoming a bottleneck - the bottleneck is still the transistor switching so simply moving to ULK, would not yield a 15% improvement. 

AMD claimed a 40% transistor improvement from 90nm to 65nm, yet 65nm K8 came out at speeds slower than 90nm K8... switching speed can result in higher clocks, but things are far more complicated than what you indicate. It is also not clear if AMD is claiming 15% switching improvement ' out of the box' or when the technology reaches maturity which could be several quarters after the initial launch as AMD uses a CTI approach.

I understand that this is not the most technical site, but your article is riddled with mistakes and I hope you post this comment so people can understand things a bit better. Perhaps also you should not try to interpret terminology (like gate first) that you seemingly do not understand.

AT adds: Charlie wasn't writing a thesis, he was trying to explain to the great unwashed what AMD had announced. Which, I might add, they're more likely to understand than your comment above.
We can't all be as clever as you obviously are.