TAIWANESE CHIPMAKERS, TSMC, unveiled their first 40 nanometer manufacturing process technology on Monday and said that the first wafers created by it could be expected within the next three months.

The 40 nm technology is the result of some fine tuning by the chipmaker on its previous 45 nm process. It uses a combination of 193nm immersion photolithography and extreme low-k (ELK) material. TSMC reckons that the process will produce the smallest SRAM cell size on the market, sizing up (or down rather) to a tiny 0.242µm sq. The company claims that by transitioning from 45nm to 40nm, power scaling will be reduced by up to 15 per cent. Also, the new 40nm node will apparently allow its LP and G processes to deliver a 2.35 raw gate density improvement over its 65nm process.

TSMC said that the new low power 40LP will be used for leakage sensitive applications which include portables and wireless devices, whilst its 40G will be used for CPUs, GPUs, game consoles, networking and FPGA designs, as well as a host of other consumer devices.

The 40G and LP chips will be produced at TSMC’s 12-inch factories. µ

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TSMC press release