AMD responds to Intel’s roadmap
Move along, nothing to see here
RANDY ALLEN, Corporate veep of the server and workstation division at AMD was happy to pour cold water over yesterday’s announcements from Chipzilla.
In an interview with The Inq at HP's Tech@work conference in Barcelona Allen said: “On Nehalem, Intel is catching up with what we have. Barcelona is here. It is shipping with the largest number of OEMs we’ve ever had. We have level three cache, we've had integrated memory since 2003 and high speed serial links since 2006. I don‘t think there is anything new here.”
On Dunnington, Allen said that AMD’s forthcoming Shanghai will be 45nm. “In 2009 we will have enhancement to Hypertransport with HT3, DDR3 technology and eight cores or more. We’ll have four cores by the end of the year and you can expect to see eight cores in the 2009 timeframe,” he said.
On Larrabee, pointing at The Inq’s excellent coverage from yesterday which said “Intel is not as close to producing Larrabee products as we anticipated, however. It said that the multicore architecture will include a high performance wide SIMD vector processing unit which will support a set of vector instructions including floating point arithmetic, vector memory ops and conditional instructions.” Allen said: “Whatever that is, it is not x86. This is going to cause problems for software makers. It is a whole different software model which will present big issues.”
Allen said AMD was not immune to these issues but was better positioned to address them. µ
Comments
AMD sounds like that Iraqi General
Do you guys remember that Iraqi general: http://www.rightwinged.com/images/photoshops/mushroomcloud.jpgThis is what AMD reminds me of. Nehalem will bury K10 deep into the ground. In fact Nehalem's projected performance numbers under a server environment seem to indicate a 1 to 2 generational quantum leap in performance (server and professional performance doesn't grow by the amounts we've seen on the desktop).
http://www.computerbase.de/news/hardware/prozessoren/intel/2008/februar/intel_nehalem_performance/
If I were AMD I would be honest and admit that Nehalem is the real thing and talk about addressing the performance deficit rather then ignoring it.
Unfortunately for Randy Allen..
.. it's not good when your competitor not only catches up but exceeds you.Anyone who expects or predicts that QPI will be worse than or not as good as HyperTransport is an AMD zealot. It's perfectly reasonable to conclude that QPI will be at the very least an equal to HyperTransport. Couple that with Intel's superior CPU performance and you have a recipe for not just catching up to AMD in the multi-socket server segment, but exceeding it.
I like AMD but...
I'll buy another processor of theirs when it's faster than an Intel cpu. The latest round (Phenom) is particularly pathetic. Please AMD, release another good chip! We need a pair of excellent CPU companies to keep prices in line.hyperthreading on amd?
I think you meant hypertransport :"On Dunnington Allen said that AMD’s forthcoming Shanghai will be 45nm. “In 2009 we will have enhancement to hyper threading with HT3, DDR3 technology and eight cores or more."
Please check your articles come on, i spotted it in a second. I don't mind bad spelling but this is what makes people think your tabloid IT news
Larabee
the larabee is suppose to use the equivalent of a micro Pentium cores (like 64 of them) with a slightly altered instruction set so it will be x86 for the most part but we will see this when they do the university thingbrendan le foll
So ironic that the guy that instructs the INQ on proper word usage misuses your for you're...Eminent&Imminent Hype
SSE5, Fusion, Cuda, GPCPU, native multi-cores, Itanium approach, 128 instructions versus 96, increase of parallelism by 33 percent, enhanced algorithms that will enable faster access to cache and implementing some branch prediction enhancements.How can companies which have long delays between driver updates and Bios updates, sufficiently get everything software recompiled for their new trannies? Aren't these the companies that kept falling short on chipset expectations? Looky-looky: here's a carrot and orange; now over here is a carrot and banana; we're sorry, we don't combine an orange and banana, or even all three. Maybe in the *next* generation. Now we decide to scrap fruit and do something with legumes; so get out of your head any vision of how delicious an orange and banana would be together. Humans use only 10% of their brains. What percentage of processors get used? Is that instruction set in 32 or 64 bits? Is there anyone selling optimizing compilers on a 3-party basis?
In what time reference could I expect to fully gain something from this new feature? Chip substrata applied to clock step? speeds? Smoke and the house of mirrors. BMW or Mercedes? Speed reading and the world's fastest communicative hack? Gric'ean Guru Sahib emeritus pontification? Were we comparing oranges to oranges? You can always check out those other chipperies. Forgive me your grace, but it all makes my head hurt. Did I turn off the stove? Hats off to you; the wind has taken minde.
But, but, but...
but the Inquirer IS tabloid IT news, that is why they are so awesome =DNahalem is 33% to 80% faster.
Nehalem, Bloomfield, will pack the processor and memory controller, as well as possibly more Northbridge functions such as a-partial- GPU in a multi-chip-package (MCP), will demand more substrate layers, implying a larger size of substrate Ibexpeak platform controller hub (PCH), which replaces the traditional Southbridge in the Nehalem platform, features a new system-on-chip (SoC) design Bloomfields list of NEWS is so long it would take three articles to cover all names ,yet just extra layer on each side soi; proven satistics of .33 to .80% better than best in works. Yet, in my thinking, how can you double that? you'd have two northbridges & two southbridges, plus 6 channels of memory. Its getting pretty complex, some parts will double, not all after nahalem? memory with 3 channels ddr3 is bandwidth TOPPER.BLOOMFIELD #1.Thomas Drashek
Please back this up...
To all of the idiots who say "I'll buy another processor of <AMDs> when it's faster than an Intel cpu": I'll bet a year's salary that most of you don't go out and buy Intel's fastest $1000 processor, you always purchase something less expensive and not as fast. And you will probably be able to find an AMD product that fits your price/performance requirements.Who Cares Who's fastest?
If you need a processor faster than AMD can make, then you have to buy Intel, and you'll pay. If you don't need the fastest processor, AMD probably makes one that will suit you, and possibly for a lower cost than Intel. The competition is not who makes the fastest processor, the competition is which company makes the cheapest product that suits your needs. Sure Intel makes the fastest CPUs, but until those CPUs are cheaper, AMD will continue to compete.Quantum leap?
"This is what AMD reminds me of. Nehalem will bury K10 deep into the ground. In fact Nehalem's projected performance numbers under a server environment seem to indicate a 1 to 2 generational quantum leap in performance (server and professional performance doesn't grow by the amounts we've seen on the desktop)."Have you even compare the microarchitecture between the Core and the AMD 10h?
What Nehalem (which is a modified Core) is going to look like is that it's going to look like a Phenom, with an integrated memory controller, hypertransport - sorry, QPI, and 4 Core2 cores that are issuing more instructions and have more in-flight instructions.
I'm speculating at the moment, but the reasons why Phenom can't stand clock to clock has to do with the Phenom not being able to keep the ALUs going. I've been running benchmarks on a Phenom, and it seem that the decoder is being empty fairly often - which their docs says that happens usually when the I-cache misses, or a branch mispredict.
Chances are, the prefetcher and the branch predictor is better on the core 2, and also, Core 2 keeps more instructions in-flight (96 vs 72) and issues more uops (peak of 6 uops with perfect macro-fusion vs 3 uops) and retires more uops (4 uops vs 3 uops).
Even with the Nehalem being modified to issue 4 instructions (I think this is x86 instructions), it isn't exactly going to be leaps and bounds over. Also, it is entirely possible to refine the AMD 10h for more throughput. The Phenom schedules integer and floating point separately, while the Core 2 schedules integer and floating point together. Suppose that the Phenom and Core 2 issues and retires uops at the same rate and keep the same number of uops in-flight, then Phenom may be able to better schedule code with a good mix of integer and floating point code, because the functional units are not fused together. Whereas, if you look at the architecture diagram for the Core2, it has 3 functional unit, which executes integer or floating point, and a load unit and a store unit.
In any case, I think you're overestimating how well Intel would pan out. There are some very suspicious underlying reasons as to why Intel took quite a while to integrate memory controllers, QPI, and have 4 cores on the same die. It is not entirely out of the question that AMD could fix the Phenom's deficiencies in the 45nm spin to better match their performance against Intel's offering.
"whatever that is, it's not x86"
Oh come on. Nice try to spread some FUD here, but by now (and in fact for quite a while) _lots_ of SW and games developers have been reviewing and giving inputs to the Larrabee architecture.It is hard to believe that Randy should not have seen at least the top level block diagram of the device. However, if he really has not, then good luck DAAMIT.
hmm
Brendan - maybe that is why it says HT3 - that would be HyperTransport v 3OEMs?!? How about the larger companies like HP/Dell!
OEM this and that. So delaying shipments to companies that sell large amount of servers like HP and Dell aren't pleased with Barcelona/Phenom launch in NOVEMBER.Strategies on the AMD Side
From what we´ve been able to glean thus far: AMD is putting few eggs ( tech+man hours )in the 65nm process. Thus far AMD´s 45 nm process has enough (technology ) to be interesting ( get mind-share ). AMD´s BIG push will be ( with IBM´s and partner´s help ) 32nm and BELOW. Lest we forget. AMD always seems to be able to pull rabbits ( surprising tech ) out of it´s proverbial Spider-woven hat. By the way, we just know IBM would love to be able to trump through AMD, IT´S hi-tech counterpart, Intel. Again, it´s about strategy.