ACE’S HARDWARE has pointed to details of Intel’s forthcoming “Nehalem” architecture.

It also points to information about Dunnington, apparently based on an Intel presentation, including its launch date, slated for the second half of this year.

The six-core Dunnington chip means each pair of cores supports 3MB of L2 cache, while the L3 shared cache, as reported here before, shares 16MB.

The chip has a 1066MT/s interconnect and will support SSE4, coming in an mPGA 604 socket and with a TDP less than 130W. It will be pin compatible with Tigerton.

Nehalem is projected as arriving late, supporting two, four and eight cores, representing four, eight and 16 threads. µ

See Also
Intel CSI diagram scribbled on back of fag packet
Intel’s Stoutland to have integrated memory controller
Intel Thurley has early CSI connect